公开(公告)号：US5583502A

公开(公告)日：1996-12-10

申请号：US263429

申请日：1994-06-21

申请人： Sumitaka Takeuchi ,  Toshio Kumamoto

发明人： Sumitaka Takeuchi ,  Toshio Kumamoto

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/66

CPC分类号： H03M1/108 ,  H03M1/12 ,  H03M1/66

摘要： There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D.sub.1a, D.sub.1b) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D.sub.1b, D.sub.1c) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is "L" if all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D.sub.1c) at its input. When all of the A-D converters are normal, all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.

摘要翻译： 公开了一种AD转换器测试电路，其中异或门（13a，13b）提供AD转换器（12a，12b）的输出的高位（D1a，D1b）和异或 分别为AD转换器（12b，12c）的输出的高位（D1b，D1c）和或门（13c）提供两个门的输出的逻辑和，如果 所有位（D1a，D1b，D1c）相等。 三态缓冲器（15a）在其控制端接收或门（13c）的输出，并在其输入端接收位（D1c）。 当所有A-D转换器都正常时，所有位（D1a，D1b，D1c）都相等，并被施加到三态缓冲器（15a）的输出。 当一个或一些A-D转换器异常时，三态缓冲器（15a）的输出进入高阻抗状态。 因此，A-D转换器测试电路快速判断A-D转换器是有缺陷的还是无缺陷的。

公开(公告)号：US5345237A

公开(公告)日：1994-09-06

申请号：US77932

申请日：1993-06-18

申请人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03F3/45 ,  H03M1/14 ,  H03M1/36 ,  H03M1/34

CPC分类号： H03M1/146 ,  H03F3/45071 ,  H03M1/365

摘要： The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4. Effectively an output from the emitter follower can be improved and a gain of the differential amplifier and linearity can be also improved.

摘要翻译： 本发明旨在改进差分放大器及其在A / D转换器中采用的周边部件，以提高A / D转换器的精度。 差分放大器具有由一对差分晶体管Q1和Q2，发射极电阻2a和2b以及集电极电阻2c和2d组成的放大元件。 差分放大器具有构成射极跟随器的晶体管Q3和Q4，用于将在差分放大元件中放大的输出施加到外部。 差分放大器包括具有连接到输入端子4a和4b并且串联连接到晶体管Q3和Q4的各自的基极的晶体管Q5和Q6，以及夹在晶体管Q5和Q6的发射极之间的电阻2e和2f，以便减轻任何 晶体管Q3和Q4的基极 - 发射极电压变化的影响。 有效地提高了射极跟随器的输出，并且还可以提高差分放大器的增益和线性度。

公开(公告)号：US5327134A

公开(公告)日：1994-07-05

申请号：US951116

申请日：1992-09-25

申请人： Yasuyuki Nakamura ,  Toshio Kumamoto

发明人： Yasuyuki Nakamura ,  Toshio Kumamoto

IPC分类号： H03M1/74 ,  H03M1/68 ,  H03M1/66

CPC分类号： H03M1/685 ,  H03M1/747

摘要： In order to improve linearlity of analog current outputs with respect to input digital codes in a D-A converter formed by a matrix array of unit current sources, respective current source cells forming the matrix are connected by analog ground wires (101 to 105 ) along respective rows. Analog ground wires (301, 302 ) connect left sides of the analog ground wires (102, 104) and right sides of the analog ground wires (101, 103, 105) to pads (41, 42 ) respectively, to ground the same. Thus, large-small relations of current distributions are reversed in respective rows, whereby influences by the current distributions are cancelled.

摘要翻译： 为了提高模拟电流输出相对于由单位电流源的矩阵阵列形成的DA转换器中的输入数字代码的线性，形成矩阵的各个电流源单元通过模拟地线（101至105）沿相应行 。 模拟地线（301,302）分别将模拟地线（102,104）的左侧和模拟地线（101,103,105）的右侧分别连接到接地点（41,42）上，以对其进行接地。 因此，电流分布的大小关系在各行中相反，由此抵消电流分布的影响。

公开(公告)号：US5283581A

公开(公告)日：1994-02-01

申请号：US952413

申请日：1992-09-29

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/14 ,  G06G7/14 ,  H03M1/16 ,  H03M1/74

CPC分类号： H03M1/167 ,  G06G7/14 ,  H03M1/747

摘要： An analog voltage subtracting circuit for calculating a difference between an analog input voltage and a voltage drop caused by a load includes an analog voltage generator 7 for generating an analog voltage, a load 3 having one end connected to an output of the analog voltage generator 7 and the other end connected to an output terminal 2, and a D/A converter 6 applying a positive output current Iout for generating a desired voltage drop at said the other end 4 of the load 3 and for applying a complementary output current Iout complementary to the positive output current Iout to said one end of the load 3. By this structure, a constant current of Iout+Iout flows at said one end 4 of the load 3, and therefore linear output can be provided.

摘要翻译： 用于计算模拟输入电压和由负载引起的电压降之间的差的模拟电压减去电路包括用于产生模拟电压的模拟电压发生器7，一端连接到模拟电压发生器7的输出的负载3 并且另一端连接到输出端子2和D / A转换器6，D / A转换器6施加正输出电流Iout，用于在负载3的另一端4处产生期望的电压降，并且用于施加互补的输出电流I ）与负载3的所述一端的正输出电流Iout互补。通过这种结构，Iout + I（OVS）的恒定电流在负载3的所述一端4处流动，因此可以提供线性输出。

公开(公告)号：US5138437A

公开(公告)日：1992-08-11

申请号：US587501

申请日：1990-09-24

申请人： Toshio Kumamoto ,  Shinichi Nakagawa ,  Masao Nakaya

发明人： Toshio Kumamoto ,  Shinichi Nakagawa ,  Masao Nakaya

IPC分类号： H01L27/06

CPC分类号： H01L27/0688 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device comprises a general purpose unit having a general purpose function and a specific unit for a specific use of the semiconductor integrated circuit device. In addition, the semiconductor integrated circuit device has structure in which a plurality of layers each having an integrated circuit formed therein are stacked in a three-dimensional manner. Specific unit layers are formed on the surface of the layer having the general purpose unit formed therein by different manufacturing processes.

摘要翻译： 半导体集成电路器件包括具有通用功能的通用单元和用于半导体集成电路器件的特定用途的特定单元。 此外，半导体集成电路器件具有其中形成有集成电路的多个层以三维方式堆叠的结构。 通过不同的制造工艺在具有通用单元的层的表面上形成特定的单位层。

公开(公告)号：US5055820A

公开(公告)日：1991-10-08

申请号：US461145

申请日：1990-01-04

申请人： Masatoshi Kimura ,  Toshio Kumamoto

发明人： Masatoshi Kimura ,  Toshio Kumamoto

IPC分类号： G01R33/07 ,  H01L43/06

CPC分类号： H01L43/065

摘要： A Hall device a semiconductor region embedded in a substrate, the embedded region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of the main, back and side surfaces of the substrate. A pair of current electrodes are formed of first highly doped regions embedded in the substrate respectively (i) between the main surfaces of the substrate and the semiconductor region and (ii) between the back surfaces of the substrate and semiconductor region so as to sandwich the semiconductor region between the main and back surfaces of the substrate. A pair of Hall voltage detecting electrodes are formed of second highly doped regions embedded in the substrate, respectively between side surfaces of the substrate and semiconductor region. The substrate can be made of SiO.sub.2 to increase electrical isolation between the electrodes.

摘要翻译： 一个霍尔器件，嵌入在衬底中的半导体区域，所述嵌入区域具有相反的主表面和背面，以及一对与所述衬底的主表面，后表面和侧表面平行并与之隔开的侧表面。 一对电流电极分别由衬底和半导体区域的主表面和（ii）衬底和半导体区域的背面之间分别（i）嵌入衬底中的第一高度掺杂区域形成，以便将衬底 半导体区域在基板的主表面和背表面之间。 一对霍尔电压检测电极分别由衬底中的第二高度掺杂区域形成，分别位于衬底和半导体区域的侧表面之间。 衬底可以由SiO 2制成以增加电极之间的电隔离。

公开(公告)号：US5041884A

公开(公告)日：1991-08-20

申请号：US596069

申请日：1990-10-11

申请人： Toshio Kumamoto ,  Hiroyuki Kouno

发明人： Toshio Kumamoto ,  Hiroyuki Kouno

IPC分类号： H01L27/06 ,  H01L29/786

CPC分类号： H01L27/0688 ,  H01L29/78642 ,  H01L29/78648 ,  H01L2924/0002

摘要： The inventive multilayer semiconductor integrated circuit has a columnar semiconductor region provided between adjacent two layers and a control electrode provided in the vicinity of the columnar semiconductor region. The transference of a signal between the adjacent two layers is carried out through the columnar semiconductor region the electric conductivity of which is controlled by a control signal applied to the control electrode. That is, the area corresponding to the columnar semiconductor region functions as an active element.

摘要翻译： 本发明的多层半导体集成电路具有设置在相邻的两层之间的柱状半导体区域和设置在柱状半导体区域附近的控制电极。 通过施加到控制电极的控制信号控制其电导率的柱状半导体区域，进行相邻两层之间的信号的转移。 也就是说，对应于柱状半导体区域的区域用作有源元件。

公开(公告)号：US08089136B2

公开(公告)日：2012-01-03

申请号：US12891214

申请日：2010-09-27

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US07202754B2

公开(公告)日：2007-04-10

申请号：US11280410

申请日：2005-11-17

申请人： Hiroshi Komurasaki ,  Tomohiro Sano ,  Hisayasu Sato ,  Toshio Kumamoto ,  Yasushi Hashizume

发明人： Hiroshi Komurasaki ,  Tomohiro Sano ,  Hisayasu Sato ,  Toshio Kumamoto ,  Yasushi Hashizume

IPC分类号： H03B5/18

CPC分类号： H03B5/1847 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1265 ,  H03B5/1268

摘要： An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.

摘要翻译： 振荡电路由包括电感可变部分和电容元件的L负载差分电路和由N沟道MOS晶体管形成的正反馈电路构成的差分LC谐振电路形成。 电感可变部被配置为通过选择布置在螺旋互连层上的多个任意位置和输入/输出端之间的多个开关电路来改变电感，从而可以控制振荡频率。 当耦合在第一输入/输出端子之间的开关电路之间的开关电路与开关电路一起导通时，电感可变部分形成电感器对。

公开(公告)号：US20060175679A1

公开(公告)日：2006-08-10

申请号：US11384244

申请日：2006-03-21

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.