公开(公告)号：US20100046652A1

公开(公告)日：2010-02-25

申请号：US12544288

申请日：2009-08-20

申请人： Hidetoshi KAWAUCHI ,  Yuken Goto ,  Takuya Okamoto ,  Toshiyuki Miyauchi

发明人： Hidetoshi KAWAUCHI ,  Yuken Goto ,  Takuya Okamoto ,  Toshiyuki Miyauchi

IPC分类号： H04L27/28 ,  H04L27/00

CPC分类号： H04L25/0234 ,  H04L5/0007 ,  H04L5/0048 ,  H04L25/0216 ,  H04L25/022 ,  H04L25/03159 ,  H04L27/2605 ,  H04L27/2647 ,  H04L27/2657 ,  H04L27/2662 ,  H04L2025/03414

摘要： A receiving device includes: a pilot extracting section; a first estimating section; a second estimating section; a third estimating section; a distortion correcting section; and a filter controlling section.

摘要翻译： 接收装置包括：导频提取部分; 第一个估计部分; 第二估计部分; 第三估计部分; 失真校正部; 和滤波器控制部。

公开(公告)号：US20060120244A1

公开(公告)日：2006-06-08

申请号：US10532858

申请日：2004-07-05

申请人： Toshiyuki Miyauchi ,  Yasuhiro Iida ,  Yuji Shinohara

发明人： Toshiyuki Miyauchi ,  Yasuhiro Iida ,  Yuji Shinohara

IPC分类号： G11B5/09

CPC分类号： G11B20/1426 ,  G11B20/10009 ,  G11B20/18 ,  G11B2020/1453 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/6343

摘要： The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoder 181 performs SISO decoding on a signal supplied from a PR-SISO decoder 81 by using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding table 201 of a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decoder 84 via a deinterleaver 83. The turbo decoder 84 performs turbo decoding on the signal output from the 17PP-SISO decoder 181. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.

摘要翻译： 本发明涉及一种解码装置和方法，程序存储介质和程序，其允许根据可变长度表编码的调制码的高性能解码。 17PP-SISO解码器181通过使用维特比解码算法或BCJR解码算法对由PR-SISO解码器81提供的信号执行SISO解码，所述维特比解码算法或BCJR解码算法根据以一对一的方式对应的路径表示， 涉及根据17PP码的编码表201的整个编码处理中的整体转换。 结果SISO解码信号经由解交织器83提供给turbo解码器84. turbo解码器84对从17PP-SISO解码器181输出的信号进行turbo解码。本发明可以应用于用于 在诸如高密度光盘的存储介质上记录/再现信号。

公开(公告)号：US06993703B2

公开(公告)日：2006-01-31

申请号：US09875310

申请日：2001-06-06

申请人： Toshiyuki Miyauchi

发明人： Toshiyuki Miyauchi

IPC分类号： H03M13/03

CPC分类号： H03M13/3911

摘要： A decoder for performing log-sum corrections by means of a linear approximation, putting stress on speed, with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder includes a linear approximation circuit that computes the log-sum corrections using the function F=−a P−Q+b, where the coefficient −a represents the gradient of the function and the coefficient b represents, the intercept and are expressed by a power exponent of 2.

摘要翻译： 一种解码器，用于通过线性近似执行对数和校正，将压力施加在速度上，并且具有减小的电路尺寸，而不会不利地影响电路的解码性能。 解码器包括线性近似电路，其使用函数F = -a P-Q + b计算对数和校正，其中系数-a表示函数的梯度，系数b表示截距，并且由 幂指数为2。

公开(公告)号：US06732322B1

公开(公告)日：2004-05-04

申请号：US09381661

申请日：1999-11-23

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori

IPC分类号： H03M1300

CPC分类号： G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/04 ,  G11C29/00 ,  G11C29/42 ,  H03M13/15

摘要： This invention relates to a memory apparatus or the like adaptable to a multi-value recording flash memory and others. A flash memory 10 is designed for 16-value (4-bit) recording. For a write operation, the encoder (12) converts input data Din into an abbreviated Reed-Solomon code to provide write data WD. The converter (13) converts the write data WD into four-bit parallel data. The converted data are fed and written to the each memory cell constituting cell arrays (11) successively. For a read operation, the converter (14) converts read data RD from the cell arrays (11) into one-byte (8-bit) parallel data and supplies the converted data to the decoder (15) for error correction in units of bytes, whereby output data Dout is obtained. Since the Reed-Solomon code is used, sufficient performance with a limited number of errors to be corrected can be obtained.

摘要翻译： 本发明涉及适用于多值记录闪存等的存储装置等。 闪存10被设计用于16值（4位）记录。 对于写入操作，编码器（12）将输入数据Din转换为缩写的Reed-Solomon码，以提供写入数据WD。 转换器（13）将写入数据WD转换为四位并行数据。 将转换后的数据依次送入构成单元阵列（11）的各存储单元。 对于读取操作，转换器（14）将来自单元阵列（11）的读取数据RD转换成一个字节（8位）并行数据，并将转换的数据提供给解码器（15）以用于以字节为单位进行纠错 ，从而获得输出数据Dout。 由于使用里德 - 所罗门码，因此可以获得具有有限数量的要纠正的错误的足够的性能。

公开(公告)号：US06668026B1

公开(公告)日：2003-12-23

申请号：US09578582

申请日：2000-05-25

申请人： Toshiyuki Miyauchi

发明人： Toshiyuki Miyauchi

IPC分类号： H04L2706

CPC分类号： H03M13/4176 ,  H03M13/4153

摘要： A path memory and likelihood update circuit 16 provided in a two-step SOVA decoder includes eight RAMs 32a, 32b, . . . , 32h to store path selection information indicative of a selection of a most likely path in each state of an input convolutional code, a trace result memory circuit 34 to store the result of most likely path tracing and output it as delay trace result signal s42, a most likely path &Dgr; memory circuit 35 to select and store a metric difference for the most likely path based on the delay trace result signal s42 and output it as delay most likely &Dgr; signal s43, and a minimum &Dgr; memory circuits 37a and 37b to store a minimum value of the metric difference for the most likely path in each state of the convolutional code based on the delay trace result signal s42 and delay most likely &Dgr; signal s43.

摘要翻译： 设置在两步SOVA解码器中的路径存储器和似然更新电路16包括八个RAM 32a，32b。 。 。 32h，以存储指示输入卷积码的每个状态中最可能的路径的选择的路径选择信息;跟踪结果存储电路34，用于存储最可能的路径跟踪的结果，并将其输出为延迟跟踪结果信号s42; 最可能的路径Delta存储器电路35，用于基于延迟跟踪结果信号s42选择并存储最可能的路径的度量差，并将其输出为延迟最可能的Delta信号s43，以及最小的Delta存储器电路37a和37b存储 基于延迟跟踪结果信号s42和延迟最可能的ΔΣ信号s43，卷积码的每个状态中最可能的路径的度量差的最小值。

公开(公告)号：US06651215B2

公开(公告)日：2003-11-18

申请号：US09215453

申请日：1998-12-17

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori

IPC分类号： H03M1341

CPC分类号： H03M13/4176 ,  H03M13/4161

摘要： Three dual-port RAMs of the number of bits=8 and the number of words=4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained.

摘要翻译： 在路径存储器电路中提供了位数= 8和字数= 4的三个双端口RAM。 根据控制电路的控制，每个时钟将路径选择信息依次写入三个RAM。 另一方面，根据控制电路的控制，每个时钟从RAM读出路径选择信息，作为读取路径选择信息等输入到追踪电路。 跟踪电路基于由控制电路形成的读取路径选择信息和跟踪起始状态信息，执行多达三次的跟踪操作。 基于跟踪结果，获得后续时钟中的解码数据和跟踪开始状态。

公开(公告)号：US5189106A

公开(公告)日：1993-02-23

申请号：US814774

申请日：1991-12-30

申请人： Toshifumi Morimoto ,  Takaaki Hattori ,  Noboru Ikegami ,  Hirofumi Nishibu ,  Toshiyuki Miyauchi ,  Kunimichi Kubo

发明人： Toshifumi Morimoto ,  Takaaki Hattori ,  Noboru Ikegami ,  Hirofumi Nishibu ,  Toshiyuki Miyauchi ,  Kunimichi Kubo

IPC分类号： C08L23/00 ,  C08L23/04 ,  C08L23/06 ,  C08L23/08

CPC分类号： C08L23/0815 ,  C08L2205/02

摘要： A polyethylene composition which has excellent flow characteristics and mechanical properties, especially low temperature mechanical properties as well as thermal stability, elasticity and workability for molding. The polyethylene composition comprises 20 to 80 wt. % of an ethylene-.alpha.-olefin copolymer of higher molecular weight having (a) intrinsic viscosity (.eta..sub.1) of 1.2 to 9.0 dl/g, (b) density (d.sub.1) of 0.890 to 0.935 g/cm.sup.3 (c) a specific areal ratio calculated with an elution temperature-eluate volume curve in elution fractionation, and (d) a specific quantity of the content which is soluble in 25.degree. C. o-dichlorobenzene, and 80 to 20 wt. % of ethylene homopolymer or ethylene-.alpha.-olefin copolymer of lower molecular weight having (e) intrinsic viscosity (.eta..sub.2) of 0.2 to 1.6 dl/g, (f) density (d.sub.2) of 0.890 to 0.980 g/cm.sup.3 and, wherein the above (.eta..sub.1) is larger than (.eta..sub.2), and the prepared composition has an intrinsic viscosity (.eta.) of 0.77 to 5.2 dl/g, a density (d) of 0.890 to 0.950 g/cm.sup.3 and a specific N-value of 1.7 to 3.5.

摘要翻译： 具有优异的流动特性和机械性能，特别是低温机械性能以及热稳定性，弹性和成型加工性的聚乙烯组合物。 聚乙烯组合物包含20至80wt。 （a）特性粘度（η）为1.2〜9.0dl / g，（b）密度（d1）为0.890〜0.935g / cm 3的高分子量乙烯-α-烯烃共聚物（c）特定粘度 在洗脱分级中用洗脱温度 - 洗脱液体积曲线计算的面积比，和（d）可溶于25℃邻二氯苯的含量的特定量，以及80-20重量％ （e）特性粘度（η2）为0.2〜1.6dl / g的乙烯均聚物或乙烯-α-烯烃共聚物，（f）密度（d2）为0.890〜0.980g / cm 3，其中 上述（eta 1）大于（eta 2），所制备的组合物的特性粘度（η）为0.77〜5.2dl / g，密度（d）为0.890〜0.950g / cm 3， 价值1.7到3.5。

公开(公告)号：US08539322B2

公开(公告)日：2013-09-17

申请号：US13125111

申请日：2009-10-27

申请人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

发明人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

IPC分类号： H03M13/03

CPC分类号： H03M13/2909 ,  G11B20/1833 ,  G11B20/1866 ,  G11B20/1876 ,  G11B2020/1853 ,  G11B2220/2516 ,  G11B2220/2537 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2778 ,  H03M13/2957

摘要： The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code.A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND×NB×NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC−ND)×NB×NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

摘要翻译： 数据处理装置和方法技术领域本发明涉及数据处理装置和方法，以及使得可以相对于产品代码的两个代码散布突发错误的程序。 分块交织器执行交织A，其是以列方向的顺序输入数据作为一个方向的过程，并且按照向右对角线向下的方向读取数据，NB位由NB位（= 相对于产品代码的ND×NB×NA比特来逐块地）。 接下来，块式交织器执行交织B，其是以列方向的顺序输入数据作为一个方向的处理，并且以行方向的顺序读取数据作为另一方向，NB位由NB位 相对于代表由P表示的内码的奇偶校验部分的（NC-ND）×NB×NA比特。 本发明可以应用于例如记录/再现装置。

公开(公告)号：US08401126B2

公开(公告)日：2013-03-19

申请号：US11473126

申请日：2006-06-23

申请人： Toshiyuki Miyauchi ,  Yuichi Mizutani

发明人： Toshiyuki Miyauchi ,  Yuichi Mizutani

IPC分类号： H04B1/66

CPC分类号： H03M13/4176 ,  H03M13/4169 ,  H03M13/6502

摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.

摘要翻译： 本发明可以减少跟踪时的功耗。 本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元 其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元， 路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域 对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域 在各个时间点读取数据，以停止从指定的子区域读取数据。

公开(公告)号：US07689888B2

公开(公告)日：2010-03-30

申请号：US11344048

申请日：2006-02-01

申请人： Makiko Kan ,  Toshiyuki Miyauchi

发明人： Makiko Kan ,  Toshiyuki Miyauchi

IPC分类号： H03M13/00

CPC分类号： H03M13/1191 ,  H03M13/132 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/3746 ,  H03M13/453

摘要： A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding. The invention is applied to an error correction system.

摘要翻译： 公开了一种解码装置和方法，通过该解码装置和方法抑制了解码器错误发生概率并且可以实现高解码性能。 ABP解码装置将奇偶校验矩阵对角化，更新LLR值，解码LLR值，然后将通过解码获得的解码字添加到解码字列表。 ABP解码装置将解码过程作为内部重复解码重复预定次数。 此外，当ABP解码装置连续地改变LLR值的优先级的初始值时，将内部重复解码重复预定次数的外部重复解码。 然后，ABP解码装置从通过重复的内部重复解码获得的解码字列表内选择最佳一个解码字。 本发明应用于纠错系统。