公开(公告)号：US08437426B2

公开(公告)日：2013-05-07

申请号：US12567856

申请日：2009-09-28

申请人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

发明人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

IPC分类号： H04B1/38 ,  H04N7/12 ,  H04L27/00

CPC分类号： H04L27/2662 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2656 ,  H04L27/2665

摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。

公开(公告)号：US20090158127A1

公开(公告)日：2009-06-18

申请号：US12335802

申请日：2008-12-16

申请人： Toshiyuki MIYAUCHI ,  Masayuki Hattori ,  Takashi Yokokawa

发明人： Toshiyuki MIYAUCHI ,  Masayuki Hattori ,  Takashi Yokokawa

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/15 ,  H03M13/1515 ,  H03M13/45

摘要： Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

摘要翻译： 本发明公开了一种对线性块码执行软判决解码的解码装置，该装置包括：硬判决解码器，被配置为使用硬判决解码算法对接收到的字执行硬判决解码; 以及软判决解码器，其被配置为仅在硬判决解码器在硬判决解码中已经失败的接收到的字上执行软判决算法的软判决解码。

公开(公告)号：US06765507B2

公开(公告)日：2004-07-20

申请号：US10428905

申请日：2003-05-02

申请人： Takashi Yokokawa ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kohei Yamamoto

发明人： Takashi Yokokawa ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kohei Yamamoto

IPC分类号： H03M700

CPC分类号： H03M13/29 ,  H03M13/258 ,  H03M13/2771 ,  H03M13/2972

摘要： An encoding device in a data transmission/reception system includes a first convolutional encoder that encodes an outer code, an interleaver that permutes input data, a second convolutional encoder that encodes an inner code, and a muti-level modulation mapping circuit that performs signal-point mapping based on eight-phase shift keying. When the encoding device uses the second convolutional encoder having two or more memories, the first convolutional encoder uses, as the outer code, a code with a minimum output distance greater than the maximum input distance at which the minimum-distance inner code is generated.

摘要翻译： 数据发送/接收系统中的编码装置包括：对外部码进行编码的第一卷积编码器，对输入数据进行置换的交织器;对内部编码进行编码的第二卷积编码器;以及多电平调制映射电路， 基于八相移键控的点映射。 当编码装置使用具有两个或更多个存储器的第二卷积编码器时，第一卷积编码器使用具有大于产生最小距离内码的最大输入距离的最小输出距离的代码作为外码。

公开(公告)号：US06732322B1

公开(公告)日：2004-05-04

申请号：US09381661

申请日：1999-11-23

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori

IPC分类号： H03M1300

CPC分类号： G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/04 ,  G11C29/00 ,  G11C29/42 ,  H03M13/15

摘要： This invention relates to a memory apparatus or the like adaptable to a multi-value recording flash memory and others. A flash memory 10 is designed for 16-value (4-bit) recording. For a write operation, the encoder (12) converts input data Din into an abbreviated Reed-Solomon code to provide write data WD. The converter (13) converts the write data WD into four-bit parallel data. The converted data are fed and written to the each memory cell constituting cell arrays (11) successively. For a read operation, the converter (14) converts read data RD from the cell arrays (11) into one-byte (8-bit) parallel data and supplies the converted data to the decoder (15) for error correction in units of bytes, whereby output data Dout is obtained. Since the Reed-Solomon code is used, sufficient performance with a limited number of errors to be corrected can be obtained.

摘要翻译： 本发明涉及适用于多值记录闪存等的存储装置等。 闪存10被设计用于16值（4位）记录。 对于写入操作，编码器（12）将输入数据Din转换为缩写的Reed-Solomon码，以提供写入数据WD。 转换器（13）将写入数据WD转换为四位并行数据。 将转换后的数据依次送入构成单元阵列（11）的各存储单元。 对于读取操作，转换器（14）将来自单元阵列（11）的读取数据RD转换成一个字节（8位）并行数据，并将转换的数据提供给解码器（15）以用于以字节为单位进行纠错 ，从而获得输出数据Dout。 由于使用里德 - 所罗门码，因此可以获得具有有限数量的要纠正的错误的足够的性能。

公开(公告)号：US06651215B2

公开(公告)日：2003-11-18

申请号：US09215453

申请日：1998-12-17

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori

IPC分类号： H03M1341

CPC分类号： H03M13/4176 ,  H03M13/4161

摘要： Three dual-port RAMs of the number of bits=8 and the number of words=4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained.

摘要翻译： 在路径存储器电路中提供了位数= 8和字数= 4的三个双端口RAM。 根据控制电路的控制，每个时钟将路径选择信息依次写入三个RAM。 另一方面，根据控制电路的控制，每个时钟从RAM读出路径选择信息，作为读取路径选择信息等输入到追踪电路。 跟踪电路基于由控制电路形成的读取路径选择信息和跟踪起始状态信息，执行多达三次的跟踪操作。 基于跟踪结果，获得后续时钟中的解码数据和跟踪开始状态。

公开(公告)号：US07051270B2

公开(公告)日：2006-05-23

申请号：US10110670

申请日：2001-08-20

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

IPC分类号： H03M13/03 ,  H03M13/00

CPC分类号： H03M13/3905 ,  H03M13/258 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/2972 ,  H03M13/6337 ,  H03M13/6577 ,  H03M13/658

摘要： A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×Iλt and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

摘要翻译： 接收作为输入的概率信息的解码器。 该概率信息是通过将通过接收值y T 与预定系数AMP乘以获得的信道值除以第一加法系数C SUB来获得的，以用于调节 通过将先验概率信息APP＆lt; T＆gt;＆lt;＆gt;＆lt; T＆gt;获得的概率信息1 / C A xAPP＆lt; SUB>通过第二加法系数C A A A的倒数，用于将先验概率信息APP 的振幅调整到软输出解码电路。 可以是大规模集成电路的软输出解码电路生成日志软输出C 1和/或外部信息1 / C＆lt; 使用用于调节软输出解码电路内部的算术运算幅度的加法系数的XEXT。

公开(公告)号：US20060015791A1

公开(公告)日：2006-01-19

申请号：US10523452

申请日：2004-05-28

申请人： Atsushi Kikuchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kazuo Watanabe ,  Makiko Kan

发明人： Atsushi Kikuchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kazuo Watanabe ,  Makiko Kan

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1836 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936

摘要： The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

摘要翻译： 本发明涉及适用于对通过使用环R上的线性码编码的编码数据进行解码的解码方法和解码器，程序，记录和再现装置和方法以及再现装置和方法。 低密度处理单元执行奇偶校验矩阵低密度处理，对获得的接收字中包含的奇偶校验矩阵的行进行线性组合，并根据线性组合结果生成奇偶校验矩阵，从而减少 在步骤S21中用于解码的奇偶校验矩阵的密度。然后，在步骤S22，LDPC解码单元通过使用通过使用密度减小的奇偶校验矩阵的和乘积算法（SPA）来执行解码 在步骤S2执行的处理。在步骤S22的处理完成的情况下，LDPC解码单元完成接收字的解码。 本发明可以用于纠错系统。

公开(公告)号：US06798593B2

公开(公告)日：2004-09-28

申请号：US09814548

申请日：2001-03-22

申请人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

发明人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

IPC分类号： G11B509

CPC分类号： H03M13/2957 ,  G11B20/10194 ,  G11B20/1426 ,  G11B20/1833 ,  G11B20/1866 ,  G11B2020/1434 ,  G11B2020/1446 ,  H03M13/6325

摘要： A magnetic recording and/or reproducing apparatus which achieves high performance encoding and high efficiency decoding to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction coding input data and an interleaver 52 for scrambling the sequence of data supplied from the error correction coder 51. The magnetic recording and/or reproducing apparatus 50 also includes, in its reproducing system, s modulation and error correction turbo decoder 64 provided with a deinterleaver for scrambling and re-arraying the sequence of the input data such as to restore the sequence of input data re-arrayed by the interleaver 52 to an original bit sequence, an error correction soft decoder for decoding data supplied from the deinterleaver and with a second interleaver for scrambling and re-arraying the sequence of data given as a difference between data output from the error correction soft decoder and data output from the deinterleaver.

摘要翻译： 一种实现高性能编码和高效率解码以降低解码错误率的磁记录和/或再现装置。 磁记录和/或再现装置50在其记录系统中包括用于纠错编码输入数据的纠错编码器51和用于对从纠错编码器51提供的数据序列进行加扰的交织器52.磁记录和/ 或再现装置50在其再现系统中还包括设置有去交织器的调制和纠错turbo解码器64，用于对输入数据的序列进行加扰和重新排列，以便恢复由所述解交织器重新排列的输入数据的序列 交织器52到原始比特序列，纠错软解码器，用于对从解交织器提供的数据进行解码，以及用于第二交织器，用于加扰和重新排列作为从纠错软解码器输出的数据与数据之间的差异的数据序列 从解交织器输出。

公开(公告)号：US06360346B1

公开(公告)日：2002-03-19

申请号：US09140005

申请日：1998-08-26

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori

IPC分类号： G11C2900

CPC分类号： G11C29/42

摘要： A storage unit is provided which is capable of preventing the occurrence of readout errors even if two or more errors arise within a code, and a storage unit checking method is offered which can improve the productivity. Write data produced by BCH-encoding and compacting data s1 inputted into a flash memory, capable of correcting two errors within a code in an encoder, is written in a cell array. Data read out from the cell array 3 is error-corrected and decoded in an error correction/encoder to generate output data. In the check to be made at manufacturing (or putting on the market), examination data written in advance is successively read out by one block so that the errors within each code is counted. If the number of errors assumes 1 or less, that code is subjected to error correction, whereas the block including a code whose error number is 2 or more is treated as a defective block. The acceptance or failure is determined depending upon, for example, whether the rate of the number of defective blocks to the total number of blocks is below or not less than 1%.

摘要翻译： 提供了一种存储单元，其能够防止在代码中出现两个或更多个错误的情况下发生读出错误，并且提供可以提高生产率的存储单元检查方法。 写入通过BCH编码产生的数据和输入到闪存中的压缩数据s1，其能够校正编码器中的代码内的两个错误，被写入单元阵列中。 从单元阵列3读出的数据在误差校正/编码器中进行纠错和解码以产生输出数据。 在制造（或投放市场）的检查中，预先写入的检查数据被一个块连续地读出，从而对每个代码中的错误进行计数。 如果错误数假定为1或更小，则该代码进行错误校正，而包含错误号为2或更大的代码的块被视为缺陷块。 接收或故障根据例如有缺陷块的数量与总块数的比率是低于还是不小于1％来确定。

公开(公告)号：US20100080330A1

公开(公告)日：2010-04-01

申请号：US12567856

申请日：2009-09-28

申请人： Hidetoshi KAWAUCHI ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

发明人： Hidetoshi KAWAUCHI ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

IPC分类号： H04B1/10

CPC分类号： H04L27/2662 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2656 ,  H04L27/2665

摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。