公开(公告)号：US20150145058A1

公开(公告)日：2015-05-28

申请号：US14614733

申请日：2015-02-05

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823814 ,  H01L21/823892

Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

Abstract translation: 制造CMOS集成电路（IC）的方法包括：以第一掩蔽级别注入第一n型掺杂剂，该第一掩模级别使其上具有第一栅极堆叠的衬底表面的p区域露出，以形成用于形成n源极/ 用于IC上的多个n沟道MOS（NMOS）晶体管的至少一部分的漏极延伸区域。 以第二掩蔽电平注入p型掺杂剂，其在其上具有第二栅极堆叠的衬底表面中露出n区，以形成用于至少部分多个p沟道MOS（PMOS）晶体管的PLDD区域 IC。 第二n型掺杂剂是逆向注入的，包括通过第一栅极叠层形成用于部分NMOS晶体管的深n阱（DNwell）。 与NLDD区域相比，DNwell的深度比第一个栅极堆叠更浅。

公开(公告)号：US09024384B2

公开(公告)日：2015-05-05

申请号：US14025920

申请日：2013-09-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract translation: 形成具有至少一个PMOS晶体管的集成电路（IC）的方法包括执行PLDD注入，包括共注入铟，碳和卤素，以及硼物种，以在具有半导体表面的衬底中建立源极/漏极延伸区域 栅极结构的任一侧包括形成在半导体表面上的栅极电介质上的栅电极。 进行源极和漏极注入以建立源极/漏极区域，其中源极/漏极区域远离源极/漏极延伸区域远离栅极结构。 在源极和漏极注入之后进行源极/漏极退火。 共注入物可以选择性地仅提供到核心PMOS晶体管，并且该方法可以包括超高温退火，例如在PLDD注入之后的激光退火。

公开(公告)号：US08878310B2

公开(公告)日：2014-11-04

申请号：US13746150

申请日：2013-01-21

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/265 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

Abstract translation: 具有MOS和DEMOS晶体管的集成电路具有铟，碳，氮和卤素掺杂物中的至少一种，提高了覆盖在DEMOS晶体管沟道上的DEMOS晶体管栅极的一部分的阈值电压。 具有MOS和LDMOS晶体管的集成电路，其具有铟，碳，氮和卤素掺杂物中的至少一种，提高覆盖DEMOS晶体管沟道的LDMOS晶体管栅极的一部分的阈值电压。 用具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和DEMOS晶体管形成集成电路的方法提高了覆盖在DEMOS晶体管沟道上的DEMOS晶体管栅极的一部分的阈值电压。 用具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和LDMOS晶体管形成集成电路的方法提高了覆盖在DEMOS晶体管沟道上的LDMOS晶体管栅极的一部分的阈值电压。

公开(公告)号：US08753944B2

公开(公告)日：2014-06-17

申请号：US13766847

申请日：2013-02-14

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Hornung ,  Terry James Bordelon, Jr. ,  Amitava Chatterjee

IPC: H01L21/336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract translation: 制造金属氧化物半导体（MOS）晶体管的方法包括提供具有掺杂有第二掺杂剂类型的衬底表面的衬底和在衬底表面上的栅极堆叠，以及在衬底表面上的掩模图案，其暴露部分 用于离子注入的衬底表面。 第一种口袋植入使用具有衬底表面上的掩模图案的第二掺杂剂类型。 至少一个逆向栅极边缘二极管漏极（GDL）还原袋注入在衬底表面上使用具有掩模图案的第一掺杂剂类型。 第一口袋植入物和逆行GDL还原袋植入物进行退火。 在退火之后，第一口袋植入件提供第一袋区域，并且逆行GDL减少袋植入物提供与第一袋区域的重叠，以在第一袋区域内形成第一反向袋部分。

公开(公告)号：US12154901B2

公开(公告)日：2024-11-26

申请号：US18188812

申请日：2023-03-23

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20240304723A1

公开(公告)日：2024-09-12

申请号：US18667347

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66492

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US11764111B2

公开(公告)日：2023-09-19

申请号：US16662967

申请日：2019-10-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/822 ,  H01L21/266 ,  H01L21/265 ,  H01L27/01

CPC classification number: H01L21/822 ,  H01L21/266 ,  H01L21/26513 ,  H01L27/013

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

公开(公告)号：US20230245891A1

公开(公告)日：2023-08-03

申请号：US17589329

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Pushpa Mahalingam ,  Mahalingam Nandakumar ,  Mona Eissa ,  Corinne Gagnet ,  Christopher Whitesell

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L21/28052 ,  H01L27/088 ,  H01L29/4933 ,  H01L21/823443

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

公开(公告)号：US20230230975A1

公开(公告)日：2023-07-20

申请号：US18188812

申请日：2023-03-23

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823418 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20230141752A1

公开(公告)日：2023-05-11

申请号：US18094088

申请日：2023-01-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L29/76 ,  H01L21/8234 ,  H01L23/525 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/823475 ,  H01L23/5258 ,  H01L27/0629 ,  H01L21/823437

Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.