公开(公告)号：US20170047130A1

公开(公告)日：2017-02-16

申请号：US14824935

申请日：2015-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone ,  Yunchen Qiu ,  Sai Zhang

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C7/1006 ,  G11C7/24 ,  G11C16/22 ,  G11C16/349 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C2207/2263

Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

Abstract translation: 要写入存储器位置的数据字以多写避免（“MWA”）码字进行增量编码。 MWA码字不会将包含逻辑“0”的单位存储单元重新写入“0”状态，并且不将逻辑“1”重新写入已经写入逻辑“1”的单元。 “存储在查找表（”LUT“）中的潜在MWA代码字由差分字DELTA_D索引。 DELTA_D表示当前存储在存储器位置的数据字和要存储在存储器位置的新数据字（“NEW_D”）之间的按位差（“delta”）。 如果MWA代码字不违反多写回避原则，验证和选择逻辑将选择代表NEW_D的MWA代码字来写入。 一些实施例使用模式生成器生成MWA码字，而不是从LUT索引MWA码字。

公开(公告)号：US20170046090A1

公开(公告)日：2017-02-16

申请号：US14826183

申请日：2015-08-13

Applicant: Texas Instruments Incorporated

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone

IPC: G06F3/06 ,  G06F9/455

CPC classification number: G06F3/0634 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0685 ,  G06F8/66 ,  G06F12/0246 ,  G06F17/30188 ,  G06F2206/1014 ,  G11C17/146

Abstract: A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

Abstract translation: 用于EEPROM型设备的一次写入存储器（WOM）代码仿真的系统包括例如用于发送存储在WOM（只写存储器）设备中的数据字的主机处理器。 主机接口由WOM控制器接收用于编码的数据字。 模拟器将WOM编码数据和地址标识符编程为WOM设备的条目。 仿真器通过搜索WOM设备的当前活动页面的条目来覆盖先前编程的WOM编码数据，以定位包括搜索到的地址标识符和先前写入的WOM编码数据字的编程的WOM条目。 当先前写入的WOM编码字不能被正确覆盖时，第二WOM编码字的内容被存储在一个新条目中。 当当前活动页面基本上已满时，新条目被存储在新页面中，并且当前活动页面被块擦除。

公开(公告)号：US20160292127A1

公开(公告)日：2016-10-06

申请号：US14678939

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract translation: 具有短并行指令字的低能量加速器处理器架构的方法和装置。 集成电路包括具有数据宽度N的系统总线，其中N是正整数; 耦合到所述系统总线并被配置为执行从耦合到所述系统总线的存储器检索的指令的中央处理器单元; 以及耦合到所述系统总线并被配置为执行从低能量加速器代码存储器检索的指令字的低能量加速器处理器，所述低能量加速器处理器具有多个执行单元，所述执行单元包括加载存储单元，负载系数单元，乘法 单元和蝶形/加法器ALU单元，每个执行单元被配置为响应于从检索到的指令字解码的操作码执行操作，其中指令字的宽度等于数据宽度N.附加方法和装置 被披露。

公开(公告)号：US09361965B2

公开(公告)日：2016-06-07

申请号：US14252551

申请日：2014-04-14

Applicant: Texas Instruments Incorporated

Inventor： Jose A. Rodriguez-Latorre ,  Hugh P. McAdams ,  Manish Goel

IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C29/04

CPC classification number: G11C11/2275 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/2945

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract translation: 公开了一种操作存储器电路的方法（图8A和8B）。 该方法包括将真实数据（01）写入多个位（B0，B1）。 将第一数据状态（0）写入指示真实数据的信号位（Bi）。 读取真实数据，并将补充数据（10）写入多个位。 将第二数据状态（1）写入指示补充数据的信号位。

公开(公告)号：US20150127695A1

公开(公告)日：2015-05-07

申请号：US14072378

申请日：2013-11-05

Applicant: Texas Instruments Incorporated

Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F1/02

CPC classification number: G06F7/548

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract translation: 一种用于处理器计算第一三角函数以在操作数的某些范围使用替代三角函数的方法。 可以使用模函数来提供具有减小的范围的操作数，并且模函数可以以保持低位位的方式在多个步骤中减去。

公开(公告)号：US20150121043A1

公开(公告)日：2015-04-30

申请号：US14067343

申请日：2013-10-30

Applicant: Texas Instruments Incorporated

Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F9/30

CPC classification number: G06F17/17 ,  G06F7/483 ,  G06F7/544 ,  G06F9/3001

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract translation: 公开了用于执行数学功能的计算机和方法。 计算机的实施例包括操作级别和驾驶员级别。 操作级别执行数学运算。 驾驶员级别包括第一查找表和第二查找表，其中第一查找表包括用于使用第一准确度来计算至少一个数学函数的第一数据。 第二查找表包括用于使用第二准确度计算至少一个数学函数的第二数据，其中第一准确度水平大于第二准确度。 驱动程序根据所选择的精度执行第一数据或第二数据。