公开(公告)号：US07087965B2

公开(公告)日：2006-08-08

申请号：US10830347

申请日：2004-04-22

申请人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

公开(公告)号：US20060088904A1

公开(公告)日：2006-04-27

申请号：US11242591

申请日：2005-10-03

申请人： Samuel Lockwood ,  Peng Tang ,  Geoff Nadolski ,  Henry Jackson ,  Zhiqiang Fang ,  Yishu Du ,  Min Yang ,  William Geiss ,  Richard Williams ,  David Burdick

发明人： Samuel Lockwood ,  Peng Tang ,  Geoff Nadolski ,  Henry Jackson ,  Zhiqiang Fang ,  Yishu Du ,  Min Yang ,  William Geiss ,  Richard Williams ,  David Burdick

IPC分类号： C12P23/00 ,  C07C45/45

CPC分类号： C07C403/24 ,  C07B2200/07 ,  C07B2200/09 ,  C07C29/143 ,  C07C45/298 ,  C07C45/511 ,  C07C45/61 ,  C07C45/64 ,  C07C45/673 ,  C07C45/70 ,  C07C45/71 ,  C07C47/21 ,  C07C49/713 ,  C07C49/753 ,  C07C403/08 ,  C07C2601/16 ,  C07D319/06 ,  C07F7/188 ,  C07F7/1892 ,  C07F9/113 ,  C07F9/5442 ,  C12P23/00 ,  C07C49/603 ,  C07C33/02 ,  C07C35/08 ,  C07C35/21

摘要： A method used for synthesizing intermediates for use in the synthesis of carotenoids and carotenoid analogs, and/or carotenoid derivatives. In some embodiments, the invention includes methods for synthesizing optically active intermediates useful for the synthesis of optically active carotenoids. Synthesis of optically active carotenoids, in one embodiment, may be accomplished by forming an optically active dihydroxy ketone intermediate from ketoisopherone. The optically active dihydroxy ketone intermediate may be converted into optically active astaxanthin derivatives.

摘要翻译： 用于合成用于合成类胡萝卜素和类胡萝卜素类似物的中间体和/或类胡萝卜素衍生物的方法。 在一些实施方案中，本发明包括用于合成可用于合成光学活性类胡萝卜素的光学活性中间体的方法。 在一个实施方案中，光学活性类胡萝卜素的合成可以通过从酮酮中形成光学活性的二羟基酮中间体来完成。 光学活性的二羟基酮中间体可以转化成光学活性的虾青素衍生物。

公开(公告)号：US07023055B2

公开(公告)日：2006-04-04

申请号：US10696634

申请日：2003-10-29

申请人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

发明人： Meikei Ieong ,  Alexander Reznicek ,  Min Yang

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/76254 ,  H01L21/823807

摘要： A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

公开(公告)号：US06946696B2

公开(公告)日：2005-09-20

申请号：US10328285

申请日：2002-12-23

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01C27/148

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US20050145837A1

公开(公告)日：2005-07-07

申请号：US10980220

申请日：2004-11-03

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

公开(公告)号：US06911383B2

公开(公告)日：2005-06-28

申请号：US10604097

申请日：2003-06-26

申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/3205

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

公开(公告)号：US20050070077A1

公开(公告)日：2005-03-31

申请号：US10967398

申请日：2004-10-18

申请人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

发明人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08 ,  H01L29/04

CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

公开(公告)号：US06830962B1

公开(公告)日：2004-12-14

申请号：US10634446

申请日：2003-08-05

申请人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

发明人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

IPC分类号： H01L2100

CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

公开(公告)号：US06815278B1

公开(公告)日：2004-11-09

申请号：US10647395

申请日：2003-08-25

申请人： Meikei Ieong ,  Min Yang

发明人： Meikei Ieong ,  Min Yang

IPC分类号： H01L218234

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/78654 ,  H01L29/78684

摘要： The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer. A semiconductor material is epitaxial grown in the opening and then various etching and etch back processing steps are used in forming the SOI substrate.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供了最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 通过将开口形成为至少包括具有不同晶体取向的第一半导体层和第二半导体层的结构，形成SOI衬底。 开口延伸到第一半导体层。 半导体材料在开口中外延生长，然后在形成SOI衬底中使用各种蚀刻和回蚀加工步骤。

公开(公告)号：US5445993A

公开(公告)日：1995-08-29

申请号：US67834

申请日：1993-05-27

申请人： Hyung S. Ahn ,  Min S. No ,  Sang K. Si ,  Won T. Choi ,  Joo O. Seo ,  Jin H. Lim ,  Min Yang

发明人： Hyung S. Ahn ,  Min S. No ,  Sang K. Si ,  Won T. Choi ,  Joo O. Seo ,  Jin H. Lim ,  Min Yang

IPC分类号： H01S5/00 ,  H01S5/042 ,  H01S5/34 ,  H01L21/20

CPC分类号： H01L33/0062

摘要： A semiconductor laser diode includes a semiconductor substrate, an active layer having a double hetero structure formed on the semiconductor substrate, a first quantum well layer formed between the active layer and the current confinement layer, a second quantum well layer formed on the active layer corresponding to the current injection groove, and a clad layer having its flat surface formed on the current injection groove and the current confinement layer. A method for manufacturing the semiconductor laser diode includes the steps of forming an active layer having a double hetero structure on the semiconductor substrate, selectively forming a current confinement layer on the active layer to form a current injection groove, forming a clad layer having its flat surface on the current injection groove and the current confinement layer.

摘要翻译： 半导体激光二极管包括半导体衬底，在半导体衬底上形成的具有双异质结构的有源层，形成在有源层和电流限制层之间的第一量子阱层，形成在有源层上的第二量子阱层对应 以及在电流注入槽和电流限制层上形成有平坦表面的覆盖层。 一种制造半导体激光二极管的方法包括以下步骤：在半导体衬底上形成具有双异质结构的有源层，在有源层上选择形成电流限制层，形成电流注入槽，形成具有平坦的覆层 电流注入槽表面和电流限制层。