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    CATALYST-ENHANCED CHEMICAL VAPOR DEPOSITION
    42.
    发明公开
    CATALYST-ENHANCED CHEMICAL VAPOR DEPOSITION 审中-公开

    公开(公告)号：US20240213093A1

    公开(公告)日：2024-06-27

    申请号：US18145582

    申请日：2022-12-22

    Applicant: Tokyo Electron Limited

    Inventor： Kai-Hung Yu ,  Hiroak Niimi ,  Robert D. Clark ,  Tadahiro Ishizaka

    IPC: H01L21/768

    CPC classification number: H01L21/76879

    Abstract: A method for processing a substrate that includes: treating the substrate with a halogen-containing catalyst, the substrate including a semiconductor layer, a dielectric layer disposed over the semiconductor layer, a recess formed in the dielectric layer, and a layer of a first metal disposed between the dielectric layer and the semiconductor layer, the layer of the first metal being at a bottom of the recess, the halogen-containing catalyst modifying a surface of the layer of the first metal; after treating the substrate with the halogen-containing catalyst, treating the substrate with a molecular inhibitor (MI), the MI covering sidewalls of the dielectric layer in the recess; depositing a second metal over the modified surface of the layer of the first metal in the recess, where the MI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

    Selective deposition of conductive cap for fully-aligned-via (FAV)
    43.
    发明授权
    Selective deposition of conductive cap for fully-aligned-via (FAV) 有权

    公开(公告)号：US11515203B2

    公开(公告)日：2022-11-29

    申请号：US16782344

    申请日：2020-02-05

    Applicant: Tokyo Electron Limited

    Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Xinghua Sun ,  Angelique Raley

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  H01L21/311

    Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

    Method of bottom-up metallization in a recessed feature
    44.
    发明授权
    Method of bottom-up metallization in a recessed feature 有权

    公开(公告)号：US11450562B2

    公开(公告)日：2022-09-20

    申请号：US17021586

    申请日：2020-09-15

    Applicant: Tokyo Electron Limited

    Inventor： Kai-Hung Yu ,  Jodi Grzeskowiak ,  Nicholas Joy ,  Jeffrey Smith

    IPC: H01L21/768

    Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.

    Three-dimensional device and method of forming the same
    45.
    发明授权
    Three-dimensional device and method of forming the same 有权

    公开(公告)号：US10770479B2

    公开(公告)日：2020-09-08

    申请号：US16357893

    申请日：2019-03-19

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Jeffrey Smith ,  Anton deVilliers ,  Kandabara Tapily ,  Jodi Grzeskowiak ,  Kai-Hung Yu

    IPC: H01L27/118 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/768

    Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.

    Interconnect structure and method of forming the same
    47.
    发明授权
    Interconnect structure and method of forming the same 有权

    公开(公告)号：US10541174B2

    公开(公告)日：2020-01-21

    申请号：US15875442

    申请日：2018-01-19

    Applicant: Tokyo Electron Limited

    Inventor： Soo Doo Chae ,  Jeffrey Smith ,  Gerrit J. Leusink ,  Robert D. Clark ,  Kai-Hung Yu

    IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END FULLY SELF-ALIGNED INTERCONNECT PROCESS
    48.
    发明申请
    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END FULLY SELF-ALIGNED INTERCONNECT PROCESS 审中-公开

    公开(公告)号：US20190295891A1

    公开(公告)日：2019-09-26

    申请号：US16357724

    申请日：2019-03-19

    Applicant: Tokyo Electron Limited

    Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

    IPC: H01L21/768 ,  H01L21/677 ,  H01L21/67 ,  H01L21/66

    Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

    METHOD FOR PROTECTING COBALT PLUGS
    49.
    发明申请
    METHOD FOR PROTECTING COBALT PLUGS 审中-公开

    公开(公告)号：US20190259650A1

    公开(公告)日：2019-08-22

    申请号：US16277744

    申请日：2019-02-15

    Applicant: Tokyo Electron Limited

    Inventor： Sang Cheol Han ,  Soo Doo Chae ,  Kai-Hung Yu

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/532 ,  C23C16/06 ,  C23C16/56

    Abstract: Methods are described for protecting cobalt (Co) metal plugs used for making electrical connections within a semiconductor device. In one example, method includes providing a substrate containing a Co metal plug in a dielectric layer, and selectively forming a ruthenium (Ru) metal cap layer on the Co metal plug. In another example, the method includes providing a substrate containing a Co metal plug in a first dielectric layer, selectively forming a Ru metal cap layer on the Co metal plug, depositing a second dielectric layer on the Ru metal cap layer and on the first dielectric layer, etching a recessed feature in the second dielectric layer to expose the Ru metal cap layer, and performing a cleaning process that removes polymer etch residue from the Ru metal cap layer in the recessed feature.

    METHOD OF INTEGRATED CIRCUIT FABRICATION WITH DUAL METAL POWER RAIL
    50.
    发明申请
    METHOD OF INTEGRATED CIRCUIT FABRICATION WITH DUAL METAL POWER RAIL 审中-公开

    公开(公告)号：US20180350665A1

    公开(公告)日：2018-12-06

    申请号：US16001695

    申请日：2018-06-06

    Applicant: Tokyo Electron Limited

    Inventor： Soo Doo Chae ,  Kaoru Maekawa ,  Jeffrey Smith ,  Nicholas Joy ,  Gerrit J. Leusink ,  Kai-Hung Yu

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

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