公开(公告)号：US06320214B1

公开(公告)日：2001-11-20

申请号：US09209214

申请日：1998-12-11

申请人： Akihiro Matsuda ,  Yoshihisa Nagano ,  Yasuhiro Uemoto

发明人： Akihiro Matsuda ,  Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.

摘要翻译： 本发明提供一种包括半导体元件和与半导体元件相邻的虚设半导体元件的半导体器件。 当半导体元件是包括底部电极，顶部电极和电极之间的电介质层的电容器元件时，虚拟电容器元件在虚拟电极之间也具有虚拟电极和虚设电介质层。 虚拟电极被定位成使得电容器元件的顶部电极和虚拟顶部电极之间的空间处于预定范围（例如，0.3μm至14μm）。 由于在干蚀刻工艺中蚀刻离子与电容器电介质层的碰撞被抑制，因此虚拟电容器元件防止电容器介电层降解。

公开(公告)号：US06143597A

公开(公告)日：2000-11-07

申请号：US678866

申请日：1996-07-12

申请人： Akihiro Matsuda ,  Yoshihisa Nagano ,  Toru Nasu ,  Koji Arita ,  Yasuhiro Uemoto

发明人： Akihiro Matsuda ,  Yoshihisa Nagano ,  Toru Nasu ,  Koji Arita ,  Yasuhiro Uemoto

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/108

CPC分类号： H01L28/56

摘要： A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.

摘要翻译： 一种制造电容器的方法包括在第一电极上形成由铁电材料或具有高介电常数的介电材料构成的第一介电层的步骤，烧结第一介电层的步骤，形成第二介电层的步骤 第一电介质层，以及在第二电介质层上形成第二电极的步骤。 通过在具有大晶粒尺寸的第一电介质层上形成具有小晶粒尺寸的第二电介质层，电容器绝缘层的表面变平。

公开(公告)号：US5652171A

公开(公告)日：1997-07-29

申请号：US594945

申请日：1996-01-31

申请人： Yoshihisa Nagano ,  Eiji Fujii

发明人： Yoshihisa Nagano ,  Eiji Fujii

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/02071 ,  H01L21/32136 ,  H01L28/60 ,  H01L28/65

摘要： A platinum bottom electrode film, a dielectric film composed of a high permittivity dielectric material or a ferroelectric material, and a platinum top electrode film are formed on a substrate on which circuit elements and wiring are formed, and the platinum top electrode film and the dielectric film are selectively dry-etched by using etching gas containing chlorine, then plasma generated by discharging gas containing fluorine is irradiated. By this method of manufacturing a semiconductor device including a capacitor, there is almost no residual chlorine, and hence erosion of the dielectric film by residual chlorine is prevented.

摘要翻译： 在其上形成有电路元件和布线的基板上形成铂底部电极膜，由介电常数高的电介质材料或铁电体材料构成的电介质膜和铂电极膜，并且铂顶部电极膜和电介质 通过使用含有氯的蚀刻气体选择性地干蚀刻膜，然后照射通过排出含氟气体产生的等离子体。 通过这种制造包括电容器的半导体器件的方法，几乎​​没有残留的氯，因此防止了由残留氯引起的电介质膜的腐蚀。

公开(公告)号：US5527729A

公开(公告)日：1996-06-18

申请号：US412563

申请日：1995-03-29

申请人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

发明人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/40

摘要： On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

摘要翻译： 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

公开(公告)号：US5430671A

公开(公告)日：1995-07-04

申请号：US224589

申请日：1994-04-07

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device comprising bit line, word line, plate electrode, ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line, and adjusting capacitor for adjusting bit line capacitance coupled to said bit line. The adjusting capacitor is provided to increase the potential difference for reading and control occurrence of operating errors.

摘要翻译： 一种半导体存储器件，包括位线，字线，平板电极，具有第一电极和第二电极的铁电电容器，所述第二电极耦合到所述平板电极，MOS晶体管的源极耦合到所述第一电极，栅极耦合 到所述字线，并且所述漏极耦合到所述位线，以及调整电容器，用于调整耦合到所述位线的位线电容。 提供调整电容器以增加用于读取和控制操作错误发生的电位差。

公开(公告)号：US07791119B2

公开(公告)日：2010-09-07

申请号：US11693960

申请日：2007-03-30

申请人： Akihiro Odagawa ,  Yoshihisa Nagano

发明人： Akihiro Odagawa ,  Yoshihisa Nagano

IPC分类号： H01L29/94

CPC分类号： H01L45/145 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.

摘要翻译： 提供了具有与常规元件不同的构造并且与半导体制造工艺的亲和性优异且在含氢气氛下的热处理稳定性优异的电阻元件。 电阻元件包括具有两个或更多个状态的电阻层，其中电阻值不同并且可以通过施加预定电压或电流从两个或更多个状态中的一个切换到另一个状态。 电阻层包括能够形成氮化物的第一和第二元素和氮。

公开(公告)号：US20070246832A1

公开(公告)日：2007-10-25

申请号：US11693960

申请日：2007-03-30

申请人： Akihiro ODAGAWA ,  Yoshihisa Nagano

发明人： Akihiro ODAGAWA ,  Yoshihisa Nagano

IPC分类号： H01L23/48

CPC分类号： H01L45/145 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.

摘要翻译： 提供了具有与常规元件不同的构造并且与半导体制造工艺的亲和性优异且在含氢气氛下的热处理稳定性优异的电阻元件。 电阻元件包括具有两个或更多个状态的电阻层，其中电阻值不同并且可以通过施加预定电压或电流从两个或更多个状态中的一个切换到另一个状态。 电阻层包括能够形成氮化物的第一和第二元素和氮。

公开(公告)号：US06781179B2

公开(公告)日：2004-08-24

申请号：US10152774

申请日：2002-05-23

申请人： Toru Nasu ,  Yoshihisa Nagano

发明人： Toru Nasu ,  Yoshihisa Nagano

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75

摘要： The semiconductor memory device of the present invention includes: an interlayer insulating film formed on a semiconductor substrate; a contact plug formed to extend through the interlayer insulating film; and a capacitor formed on the interlayer insulating film so that an electrode of the capacitor is connected with the contact plug. The electrode has an iridium oxide film as an oxygen barrier film. The average grain size of granular crystals constituting the iridium oxide film is a half or less of the thickness of the iridium oxide film.

摘要翻译： 本发明的半导体存储器件包括：形成在半导体衬底上的层间绝缘膜; 形成为延伸穿过所述层间绝缘膜的接触插塞; 以及形成在层间绝缘膜上的电容器，使得电容器的电极与接触插塞连接。 电极具有作为氧阻隔膜的氧化铱膜。 构成氧化铱膜的粒状晶体的平均粒径为氧化铱膜的厚度的一半以下。

公开(公告)号：US06528327B2

公开(公告)日：2003-03-04

申请号：US09922782

申请日：2001-08-07

申请人： Yoshihisa Nagano ,  Toru Nasu ,  Hajime Yasuoka ,  Eiji Fujii

发明人： Yoshihisa Nagano ,  Toru Nasu ,  Hajime Yasuoka ,  Eiji Fujii

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L28/60 ,  H01L28/91

摘要： A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.

摘要翻译： 在通过基板上的钝化膜形成的接触孔中形成接触塞，使得凹部留在接触插塞上。 然后，钝化膜被干蚀刻，使得凹部的开口膨胀或凹陷的深度减小。 之后，依次形成与触点插头连接的下部电极，绝缘金属氧化物的电容绝缘膜和上部电极，制成电容器。

公开(公告)号：US06294438B1

公开(公告)日：2001-09-25

申请号：US09589520

申请日：2000-06-08

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

摘要翻译： 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。