公开(公告)号：US20210335786A1

公开(公告)日：2021-10-28

申请号：US17367447

申请日：2021-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US11088137B2

公开(公告)日：2021-08-10

申请号：US16724404

申请日：2019-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/84

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US10943993B2

公开(公告)日：2021-03-09

申请号：US16396777

申请日：2019-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.

公开(公告)号：US10692780B2

公开(公告)日：2020-06-23

申请号：US16280043

申请日：2019-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.

公开(公告)号：US10153210B1

公开(公告)日：2018-12-11

申请号：US15618131

申请日：2017-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823462 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02269 ,  H01L21/0228 ,  H01L21/823431

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a shallow trench isolation (STI) around the first fin-shaped structure; forming a first oxide layer on the first fin-shaped structure; and then forming a second oxide layer on the first oxide layer and the STI.

公开(公告)号：US09972623B1

公开(公告)日：2018-05-15

申请号：US15375177

申请日：2016-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Shou-Wei Hsieh ,  Hsin-Yu Chen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/311

CPC classification number: H01L27/092 ,  H01L21/31144 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/517

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

公开(公告)号：US09871102B2

公开(公告)日：2018-01-16

申请号：US14684443

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US09698218B2

公开(公告)日：2017-07-04

申请号：US15221617

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/02 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/324 ,  H01L21/306 ,  H01L29/10

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

公开(公告)号：US20160268375A1

公开(公告)日：2016-09-15

申请号：US14684443

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/10 ,  H01L29/423 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

Abstract translation: 半导体器件及其形成方法，该半导体器件包括单晶衬底，源/漏结构和纳米线结构。 源极/漏极结构设置在衬底上并与衬底接触。 纳米线结构连接到源极/漏极结构。

公开(公告)号：US09274416B2

公开(公告)日：2016-03-01

申请号：US14023476

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Hsin-Yu Chen ,  Kai-Lin Chuang

IPC: G03F1/72 ,  G03F1/00

CPC classification number: G03F1/72 ,  G03F1/144 ,  G03F1/36

Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.

Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。