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    Resistive random access memory structure and fabricating method of the same
    42.
    发明授权
    Resistive random access memory structure and fabricating method of the same 有权

    公开(公告)号：US11665913B2

    公开(公告)日：2023-05-30

    申请号：US17541226

    申请日：2021-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Yu Lin ,  Po-Kai Hsu ,  Chung-Yi Chiu

    IPC: H10B63/00

    CPC classification number: H10B63/30 ,  H10N70/041 ,  H10N70/066 ,  H10N70/24 ,  H10N70/826

    Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

    Semiconductor power device
    44.
    发明授权
    Semiconductor power device 有权
    半导体功率器件

    公开(公告)号：US09306045B2

    公开(公告)日：2016-04-05

    申请号：US14083551

    申请日：2013-11-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

    IPC: H01L29/66 ,  H01L29/739 ,  H01L29/08

    CPC classification number: H01L29/7395 ,  H01L29/0834

    Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

    Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。

    Method of forming Fin-FET
    45.
    发明申请
    Method of forming Fin-FET 有权
    Fin-FET的形成方法

    公开(公告)号：US20150064869A1

    公开(公告)日：2015-03-05

    申请号：US14018439

    申请日：2013-09-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

    IPC: H01L29/66

    CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/6681

    Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

    Abstract translation: 本发明提供一种形成Fin-FET的方法。 在其上限定具有有源区和虚拟区的衬底。 多个第一鳍片和第二鳍片形成在有源区域中，并且在虚拟区域和有源区域中形成多个虚设翅片。 在活动区域​​中设置第一有源区域。 经修改的第一有源区通过延伸第一有源区以覆盖至少一个相邻的虚拟鳍形成。 接下来，在虚拟区域中设置第一虚拟区域。 通过组合经修改的第一有源区和第一伪区形成第一掩模布局。 通过使用第一掩模布局形成第一图案化掩模层。 对由第一图案化掩模层暴露的第一鳍片和虚拟鳍片执行第一外延工艺。

    STRUCTURE OF MIM CAPACITOR AND HEAT SINK
    47.
    发明申请
    STRUCTURE OF MIM CAPACITOR AND HEAT SINK 有权

    公开(公告)号：US20250038103A1

    公开(公告)日：2025-01-30

    申请号：US18233877

    申请日：2023-08-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

    IPC: H01L23/522 ,  H01L23/36 ,  H01L23/528

    Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.

    Memory device
    48.
    发明授权
    Memory device 有权

    公开(公告)号：US12213389B2

    公开(公告)日：2025-01-28

    申请号：US18239104

    申请日：2023-08-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

    IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

    Abstract: A memory device includes a substrate, a memory unit disposed on the substrate, a first spacer layer, and a second spacer layer. The memory unit includes a first electrode, a second electrode disposed above the first electrode, and a memory material layer disposed between the first electrode and the second electrode. The first spacer layer is disposed on a sidewall of the memory unit and includes a first portion disposed on a sidewall of the first electrode, a second portion disposed on a sidewall of the second electrode, and a bottom portion. A thickness of the second portion is greater than that of the first portion. The second spacer layer is disposed on the first spacer layer. A material composition of the second spacer layer is different from that of the first spacer layer. The bottom portion is disposed between the substrate and the second spacer layer.

    Method of removing step height on gate structure
    49.
    发明授权
    Method of removing step height on gate structure 有权

    公开(公告)号：US12211699B2

    公开(公告)日：2025-01-28

    申请号：US17857158

    申请日：2022-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

    IPC: H01L21/311 ,  H01L21/768

    Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

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