公开(公告)号：US20190081000A1

公开(公告)日：2019-03-14

申请号：US15730744

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/532 ,  H01L23/522

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US20160148816A1

公开(公告)日：2016-05-26

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一材料层; 在所述第一材料层上形成停止层; 在所述停止层上形成第二材料层; 并且进行平面化处理以去除第二材料层，停止层以及用于形成栅极层的第一材料层的一部分。

公开(公告)号：US12232425B2

公开(公告)日：2025-02-18

申请号：US18515273

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US12201032B2

公开(公告)日：2025-01-14

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H10N50/85 ,  H10B61/00 ,  H10N50/80 ,  H10N50/01

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US11917923B2

公开(公告)日：2024-02-27

申请号：US17242322

申请日：2021-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Si-Han Tsai ,  Shun-Yu Huang ,  Chen-Yi Weng ,  Ju-Chun Fan ,  Che-Wei Chang ,  Yi-Yu Lin ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Ya-Jyuan Hung

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H01L27/22 ,  H01L43/12

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

公开(公告)号：US20240065108A1

公开(公告)日：2024-02-22

申请号：US17944242

申请日：2022-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Po-Kai Hsu

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L27/222 ,  H01L43/10

Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.

公开(公告)号：US11849648B2

公开(公告)日：2023-12-19

申请号：US17341417

申请日：2021-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  H01L29/82 ,  G11C11/16 ,  G11C5/06 ,  H10N50/01 ,  H10N50/10 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

公开(公告)号：US11616193B2

公开(公告)日：2023-03-28

申请号：US17338632

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US11522127B2

公开(公告)日：2022-12-06

申请号：US17204937

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US20220310697A1

公开(公告)日：2022-09-29

申请号：US17228720

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.