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    Method and apparatuses for customizable error correction of memory
    43.
    发明授权
    Method and apparatuses for customizable error correction of memory 有权
    存储器可定制错误校正的方法和装置

    公开(公告)号：US08510628B2

    公开(公告)日：2013-08-13

    申请号：US12617661

    申请日：2009-11-12

    申请人： Ferdinando Bedeschi ,  Paolo Amato ,  Roberto Gastaldi

    发明人： Ferdinando Bedeschi ,  Paolo Amato ,  Roberto Gastaldi

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data.

    摘要翻译： 这里描述了一种用于为存储器阵列提供可定制的纠错的方法和装置。 在一个实施例中，装置包括具有用于存储数据的存储器阵列和耦合到存储器阵列的模拟到数字感测单元的存储器件。 模拟到数字感测单元感测与存储器阵列相关联的模拟信号，并将模拟信号转换成数字值的分布。 纠错码（ECC）单元从模拟数字感测单元接收数字值的分布。 可配置的非易失性查找表生成包括错误概率数据的ECC参数，并将ECC参数提供给ECC单元用于纠错。 误差概率数据具有与数字值分布相关联的误差概率值。 ECC单元执行ECC算法以使用错误概率数据提供纠错。

    METHODS FOR A PHASE-CHANGE MEMORY ARRAY
    44.
    发明申请
    METHODS FOR A PHASE-CHANGE MEMORY ARRAY 有权
    相变记忆阵列的方法

    公开(公告)号：US20140376306A1

    公开(公告)日：2014-12-25

    申请号：US13518361

    申请日：2009-12-31

    申请人： Ferdinando Bedeschi ,  Claudio Resta ,  Marco Ferraro

    发明人： Ferdinando Bedeschi ,  Claudio Resta ,  Marco Ferraro

    IPC分类号： G11C13/00

    CPC分类号： G06F3/0622 ,  G06F3/0643 ,  G06F3/0679 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C13/0097 ,  G11C13/02 ,  H01L45/04 ,  H01L45/06

    摘要： Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.

    摘要翻译： 描述了操作相变存储器阵列的方法。 一种方法包括确定要写入相变存储器阵列的图案，并且根据该图案，在相变存储器阵列上执行两个或更多个适当的复位序列以将该图案写入相变存储器阵列。 另一种方法包括在相变存储器阵列上执行设置序列并执行相变存储器阵列的适当读取以获得从执行所述设置序列导出的模式。

    Writing bit alterable memories
    45.
    发明授权
    Writing bit alterable memories 有权
    写点可变记忆

    公开(公告)号：US08760938B2

    公开(公告)日：2014-06-24

    申请号：US11906722

    申请日：2007-10-03

    申请人： Ferdinando Bedeschi ,  Claudio Resta ,  Richard Fackenthal ,  Ruili Zhang

    发明人： Ferdinando Bedeschi ,  Claudio Resta ,  Richard Fackenthal ,  Ruili Zhang

    IPC分类号： G11C7/00

    CPC分类号： G11C5/145

    摘要： A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients.

    摘要翻译： 一个可变的存储器可以包括在主存储器核心外部的周边的电流发生器。 电流可能在外围产生并被驱动到芯中。 结果，存储单元的电容降低了效果。 可以使用芯片电源电压产生电流，然后使用泵浦电压进行镜像。 在一些实施例中，镜像可以在分区级别进行比例并且在平面级上相乘。 在将电流施加到电池以适应瞬态之前可以提供延迟。

    Circuitry for reading phase-change memory cells having a clamping circuit
    46.
    发明授权
    Circuitry for reading phase-change memory cells having a clamping circuit 有权
    用于读取具有钳位电路的相变存储单元的电路

    公开(公告)号：US08259515B2

    公开(公告)日：2012-09-04

    申请号：US12491352

    申请日：2009-06-25

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

    摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

    摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

    PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE
    47.
    发明申请
    PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE 有权
    相位改变记忆装置，其中放出了所选择的比特币中的泄漏电流，以及用于在相变存储器件的所述被排列的比特中排出漏电流的方法

    公开(公告)号：US20100128517A1

    公开(公告)日：2010-05-27

    申请号：US12560235

    申请日：2009-09-15

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C5/14

    CPC分类号： G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/79

    摘要： A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage.

    摘要翻译： 相变存储器件包括位线偏置单元; 以及位线选择单元，其将所选择的位线连接到所述位线偏置单元，并且在操作状态下将所选择的位线与所述位线偏置单元断开。 位线放电单元连接到位线以排除位线中的泄漏电流。 位线放电单元具有电压调节单元和耦合在电压调节单元和相应位线之间的多个位线放电开关。 控制位线放电开关将取消选择的位线连接到电压调节单元，并将选定的位线与电压调节单元断开。 电压调节单元包括耦合在调节电压总线和参考电位线之间的PMOS晶体管。 调节电压总线连接到位线放电开关，PMOS晶体管的控制端被偏置为恒定电压。

    Circuit for Reading Memory Cells
    48.
    发明申请
    Circuit for Reading Memory Cells 有权
    读取存储单元的电路

    公开(公告)号：US20090285016A1

    公开(公告)日：2009-11-19

    申请号：US12491352

    申请日：2009-06-25

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

    摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

    摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

    Generating reference currents compensated for process variation in non-volatile memories
    49.
    发明申请
    Generating reference currents compensated for process variation in non-volatile memories 有权
    生成参考电流补偿了非易失性存储器中的工艺变化

    公开(公告)号：US20090080267A1

    公开(公告)日：2009-03-26

    申请号：US11904071

    申请日：2007-09-26

    申请人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Donze

    发明人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Donze

    IPC分类号： G11C5/14 ,  G05F3/02

    CPC分类号： G11C5/147

    摘要： In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (Iref) due to manufacturing process deviations.

    摘要翻译： 在电流参考发生器装置中，电压基准发生器级产生参考电压（Vref），并且有源元件输出级接收参考电压（Vref）并输出作为参考电压（Vref）的函数的参考电流（Iref） 。 控制级可操作地耦合到电压参考发生器级和有源元件输出级，并且控制与电压参考发生器级相关联的第一可调整参数（m）和与有源元件输出级相关联的第二可调整参数，以便 以补偿由于制造工艺偏差导致的参考电流（Iref）的值的变化。

    Semiconductor memory device with information loss self-detect capability
    50.
    发明申请
    Semiconductor memory device with information loss self-detect capability 有权
    半导体存储器件具有信息丢失自检能力

    公开(公告)号：US20070253238A1

    公开(公告)日：2007-11-01

    申请号：US11415879

    申请日：2006-05-01

    申请人： Claudio Resta ,  Ferdinando Bedeschi

    发明人： Claudio Resta ,  Ferdinando Bedeschi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/22 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0083

    摘要： A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

    摘要翻译： 一种半导体存储器件，包括多个可编程存储器单元，每个可编程存储器单元适于在至少第一状态和第二状态之间变为一个，所述多个存储器单元包括用于存储数据的存储单元，以及用于存取存储器的装置 用于阅读/修改其状态的单元格。 所述多个中的至少一个存储单元被用作检测器存储器单元，并且提供与所述至少一个检测器存储单元可操作地相关联的控制装置，所述控制装置适于建立存储在存储单元中的数据的潜在损耗 所述多个基于所述至少一个检测器存储单元的检测到的第一状态。