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41.发明授权公开(公告)号：US07391589B2
公开(公告)日：2008-06-24
申请号：US11730509
申请日：2007-04-02
CPC分类号： G11B25/043 , G11B33/08 , Y10T29/49025
摘要： A disc drive assembly is provided including a head disc assembly, a housing having a base and a cover cooperating with one another to form a chamber in which the head disc assembly is housed, and a damper structure in operative association with the housing for dampening noise and/or vibration emanated from the head disc assembly. The damper structure includes a viscoelastic damper layer and a continuous, polymeric constraining layer intimately contacting and encasing the viscoelastic damper layer. The constraining layer has a greater stiffness and higher modulus of dynamic shearing elasticity than the viscoelastic damper layer, and is molded from a high density filler and a moldable compound that is immiscible with the viscoelastic damper layer to provide a discrete interface between the constraining layer and the viscoelastic damper layer.
摘要翻译： 提供了一种盘驱动器组件，其包括头盘组件，具有基座和与彼此配合的盖的壳体，以形成其中容纳头盘组件的腔室，以及与壳体可操作地相关联的阻尼器结构，用于抑制噪音 和/或从头盘组件发出的振动。 阻尼器结构包括粘弹性阻尼层和紧密接触和包裹粘弹性阻尼层的连续聚合约束层。 约束层具有比粘弹性阻尼层更大的刚度和更高的动态剪切弹性模量，并且由高密度填料和可模制化合物模制而成，其与粘弹性阻尼层不混溶，以在约束层和 粘弹阻尼层。
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公开(公告)号：US20080116513A1
公开(公告)日：2008-05-22
申请号：US11980228
申请日：2007-10-30
IPC分类号： H01L27/092
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
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43.发明申请Isolation structures for integrated circuits and modular methods of forming the same 有权用于集成电路的隔离结构和形成其的模块化方法公开(公告)号：US20070278612A1
公开(公告)日：2007-12-06
申请号：US11444102
申请日：2006-05-31
IPC分类号： H01L29/00
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
摘要翻译： 用于半导体衬底的各种隔离结构包括形成在衬底中的沟槽，其填充有电介质材料或填充有导电材料并且沿着沟槽的壁衬有介电层。 沟槽可以与掺杂的侧壁隔离区域组合使用。 沟槽和侧壁隔离区域都可以是环形的并且包围衬底的隔离袋。 隔离结构通过不包括显着的热处理或掺杂剂扩散的模块化注入和蚀刻工艺形成，使得所得到的结构是紧凑的并且可以紧密地堆积在衬底的表面中。
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44.发明授权公开(公告)号：US07279378B2
公开(公告)日：2007-10-09
申请号：US11067248
申请日：2005-02-25
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。
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公开(公告)号：US07215012B2
公开(公告)日：2007-05-08
申请号：US10735585
申请日：2003-12-12
申请人： James Harnden , Allen K. Lam , Richard K. Williams , Anthony Chia , Chu Weibing
发明人： James Harnden , Allen K. Lam , Richard K. Williams , Anthony Chia , Chu Weibing
IPC分类号： H01L23/495 , H01L23/48 , H01L23/52
CPC分类号： H01L23/49562 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/014 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.
摘要翻译： 通过产生用于从设备的接地触点接收下焊线的至少一个补充的下焊垫部分来增强横向导电的半导体器件封装中的空间的有效利用。 补充的底部部分可以占据以前由非整体引线占据的包装的端部或侧面的区域。 通过接收衬底下焊接线，补充的双面部分允许主凹版的更大面积被具有较大面积的模具占据，从而提高了封装的空间效率。
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46.发明授权公开(公告)号：US07199970B2
公开(公告)日：2007-04-03
申请号：US10698937
申请日：2003-11-03
IPC分类号： G11B33/14
CPC分类号： G11B25/043 , G11B33/08 , Y10T29/49025
摘要： A disc drive assembly is provided including a head disc assembly, a housing having a base and a cover cooperating with one another to form a chamber in which the head disc assembly is housed, and a damper structure in operative association with the housing for dampening noise and/or vibration emanated from the head disc assembly. The damper structure includes a viscoelastic damper layer and a continuous, polymeric constraining layer intimately contacting and encasing the viscoelastic damper layer. The constraining layer has a greater stiffness and higher modulus of dynamic shearing elasticity than the viscoelastic damper layer, and is molded from a high density filler and a moldable compound that is immiscible with the viscoelastic damper layer to provide a discrete interface between the constraining layer and the viscoelastic damper layer.
摘要翻译： 提供了一种盘驱动器组件，其包括头盘组件，具有基座和与彼此配合的盖的壳体，以形成其中容纳头盘组件的腔室，以及与壳体可操作地相关联的阻尼器结构，用于抑制噪音 和/或从头盘组件发出的振动。 阻尼器结构包括粘弹性阻尼层和紧密接触和包裹粘弹性阻尼层的连续聚合约束层。 约束层具有比粘弹性阻尼层更大的刚性和更高的动态剪切弹性模量，并且由高密度填料和可模制化合物模制而成，其与粘弹性阻尼层不混溶，以在约束层和 粘弹阻尼层。
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公开(公告)号：US07135738B2
公开(公告)日：2006-11-14
申请号：US10767751
申请日：2004-01-28
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
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48.发明授权Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance 有权具有降低的导通电阻的超自对准沟槽门控DMOS的制造工艺公开(公告)号：US06756274B2
公开(公告)日：2004-06-29
申请号：US10146568
申请日：2002-05-14
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L27/0255 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/456 , H01L29/7808 , H01L29/7811
摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.
摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。
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公开(公告)号：US06750507B2
公开(公告)日：2004-06-15
申请号：US10146668
申请日：2002-05-14
IPC分类号： H01L218222
CPC分类号： H01L29/7813 , H01L27/0255 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/456 , H01L29/7808 , H01L29/7811
摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.
摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。
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公开(公告)号：USD488136S1
公开(公告)日：2004-04-06
申请号：US29173646
申请日：2003-01-03
申请人： James Harnden , Richard K. Williams , Anthony Chia , Chu Weibing , Allen K. Lam
设计人： James Harnden , Richard K. Williams , Anthony Chia , Chu Weibing , Allen K. Lam
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