公开(公告)号：US20120056261A1

公开(公告)日：2012-03-08

申请号：US13285172

申请日：2011-10-31

Applicant: James Harnden ,  Lynda Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang ,  Anthony C. Tsui ,  Hui Teng ,  Ming Zhou

Inventor： James Harnden ,  Lynda Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang ,  Anthony C. Tsui ,  Hui Teng ,  Ming Zhou

IPC: H01L29/78 ,  H01L21/56

CPC classification number: H01M10/44 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/3011 ,  H02J7/0031 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract translation: 本发明的实施例涉及一种用于双向和反向阻断电池开关的改进的封装。 根据一个实施例，两个开关在管芯封装中并排定向，而不是端对端。 该配置降低了给定模具面积的总开关电阻，通常降低电阻以避免使用后金属以满足电阻规格。 消除背面金属可以降低模具封装的整体成本，并消除与后金属制造有关的潜在故障模式。 本发明的实施例还可以允许更多的引脚连接和增加的引脚间距。 这导致用于更高电流连接的冗余连接，从而降低电阻和热阻并且最小化模具封装的制造或实施的成本。

公开(公告)号：US20070007640A1

公开(公告)日：2007-01-11

申请号：US11521885

申请日：2006-09-15

Applicant: James Harnden ,  Richard Williams ,  Anthony Chia ,  Chu Weibing

Inventor： James Harnden ,  Richard Williams ,  Anthony Chia ,  Chu Weibing

IPC: H01L23/48

CPC classification number: H01L24/48 ,  H01L23/3107 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K3/3426 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Abstract translation: 微电子器件的节省空间的封装允许每单位PC板表面积更大的功能。 在某些实施例中，具有反向鸥翼形状的引线的封装减少了由引线占据的外围覆盖区域，从而允许将封装封装的最大空间分配给封装主体和封闭的管芯。 根据本发明的封装的实施例还可以通过具有用于接收引脚端部的凹部来减小封装垂直轮廓，从而减小封装底部和PC板之间的间隙。 在封装下面提供一个线性引脚并相对于PC板略微倾斜，通过消除与J型引线的曲率半径相关联的附加间隙，进一步降低了垂直封装形状。

公开(公告)号：US07057273B2

公开(公告)日：2006-06-06

申请号：US09895478

申请日：2001-06-29

Applicant: James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

Inventor： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

IPC: H01L23/48

CPC classification number: H01L24/48 ,  H01L23/3107 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K3/3426 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

公开(公告)号：USD513608S1

公开(公告)日：2006-01-17

申请号：US29173644

申请日：2003-01-03

Applicant: James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing ,  Allen K. Lam

Designer： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing ,  Allen K. Lam

公开(公告)号：USD494939S1

公开(公告)日：2004-08-24

申请号：US29172799

申请日：2002-12-17

Applicant: James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

Designer： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

公开(公告)号：USD471165S1

公开(公告)日：2003-03-04

申请号：US29141963

申请日：2001-05-15

Applicant: Richard K. Williams ,  James Harnden ,  Anthony Chia ,  Chu Weibing

Designer： Richard K. Williams ,  James Harnden ,  Anthony Chia ,  Chu Weibing

CPC classification number: H01L2924/181 ,  H01L2924/00012

公开(公告)号：US20080111219A1

公开(公告)日：2008-05-15

申请号：US11559819

申请日：2006-11-14

Applicant: James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

Inventor： James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49541 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/206

Abstract: Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.

Abstract translation: 根据本发明的实施例涉及用于垂直导电半导体器件的封装设计，其包括与管芯的顶表面的低电阻接触。 在一个实施例中，低电阻触点可以通过使用与引线框架的一侧或者引线框架的两侧的铝带接合来建立。 根据特定实施例，垂直传导装置可以容纳在为此目的修改的四边形无引线（QFN）封装中。

公开(公告)号：USD558694S1

公开(公告)日：2008-01-01

申请号：US29240406

申请日：2005-10-11

Applicant: James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

Designer： James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

公开(公告)号：US20070134851A1

公开(公告)日：2007-06-14

申请号：US11701761

申请日：2007-02-02

Applicant: James Harnden ,  Allen Lam ,  Richard Williams ,  Anthony Chia ,  Chu Weibing

Inventor： James Harnden ,  Allen Lam ,  Richard Williams ,  Anthony Chia ,  Chu Weibing

IPC: H01L21/00

CPC classification number: H01L23/49562 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

公开(公告)号：US07215012B2

公开(公告)日：2007-05-08

申请号：US10735585

申请日：2003-12-12

Applicant: James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

Inventor： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49562 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

Abstract translation: 通过产生用于从设备的接地触点接收下焊线的至少一个补充的下焊垫部分来增强横向导电的半导体器件封装中的空间的有效利用。 补充的底部部分可以占据以前由非整体引线占据的包装的端部或侧面的区域。 通过接收衬底下焊接线，补充的双面部分允许主凹版的更大面积被具有较大面积的模具占据，从而提高了封装的空间效率。