公开(公告)号：US20080179582A1

公开(公告)日：2008-07-31

申请号：US11668208

申请日：2007-01-29

申请人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

发明人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

IPC分类号： H01L45/00

CPC分类号： H01L45/122 ,  G11C13/0004 ,  G11C2213/55 ,  H01L45/06 ,  H01L45/1675

摘要： Thin-film phase-change memories having small phase-change switching volume formed by overlapping thing films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

摘要翻译： 薄膜相变存储器具有通过重叠的物质膜形成的小的相变开关体积。 示例性实施例包括相变存储元件，包括具有电阻的第一相变层，具有电阻的第二相变层，设置在第一和第二相变层之间的绝缘层; 和具有电阻的第三相变层，并且耦合到第一和第二相变层中的每一个，桥接绝缘层并电耦合第一和第二相变层，其中第三相变层的电阻大于 第一相变层和第二相变层的电阻。

公开(公告)号：US20080137400A1

公开(公告)日：2008-06-12

申请号：US11567361

申请日：2006-12-06

申请人： Shih Hung Chen ,  Hsiang Lan Lung ,  Yi-Chou Chen

发明人： Shih Hung Chen ,  Hsiang Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C11/00 ,  H01L21/02

CPC分类号： H01L45/06 ,  G11C8/10 ,  G11C13/0004 ,  G11C2213/79 ,  H01L21/76834 ,  H01L21/76877 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory cell has thermal isolation material between a bottom electrode and a plug contact to confine heat in a memory element during programming and reset operations. In a particular embodiment, the memory element is a chalcogenide, such as GST. An electrically conductive barrier layer deposited over the contact and on sidewalls of a recess formed over the contact electrically couples the bottom electrode to the contact.

摘要翻译： 存储单元在底电极和插头触点之间具有热隔离材料，以在编程和复位操作期间将热量限制在存储元件中。 在特定实施例中，存储元件是硫属化物，例如GST。 沉积在接触件上方的形成在触点上的凹部的侧壁上的导电阻挡层将底部电极电耦合到触点。

公开(公告)号：US20070285960A1

公开(公告)日：2007-12-13

申请号：US11420107

申请日：2006-05-24

申请人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/148 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

摘要： A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

摘要翻译： 一个记忆体装置 存储元件阵列形成在半导体芯片上。 字线的并行阵列沿着第一方向延伸，将每个存储器元件连接到数据源，并行的位线阵列沿第二方向延伸，将每个存储器元件连接到数据源，第二方向形成锐角 到第一个方向。 每个位线与每个存储元件之间的连接是由具有至少两个固相的存储器材料组成的相变元件。

公开(公告)号：US20050161747A1

公开(公告)日：2005-07-28

申请号：US10764750

申请日：2004-01-26

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.

摘要翻译： 存储单元包括硫属元素随机存取存储器（CRAM）单元和CMOS电路。 CMOS电路访问CRAM单元。 CRAM单元具有通过薄膜工艺（例如，硫族化物沉积薄膜工艺）和通过等蚀刻工艺确定的横截面积。 如果需要，硫族化物结构可以与诸如二极管或选择晶体管的半导体器件串联地实现。 二极管驱动通过硫族化物结构的电流。 当通过选择晶体管的栅极端子处的电压使能时，选择晶体管驱动通过硫族化物结构的电流。 选择晶体管具有栅极端子，源极端子和漏极端子; 栅极端子可以可操作地耦合到存储器阵列的字线，源极端子可操作地耦合到存储器阵列的驱动线，并且漏极端子可以可操作地耦合到存储器阵列的位线。

公开(公告)号：US20050145984A1

公开(公告)日：2005-07-07

申请号：US10752422

申请日：2004-01-06

申请人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

发明人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

IPC分类号： G11C16/02 ,  H01L27/24 ,  H01L29/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

摘要： A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The elements thus defined may be used within chalcogenide memory cells or other semiconductor devices.

摘要翻译： 公开了一种制造相变元件的方法，该相变元件具有特别用于相变存储器单元的超小横截面积，并且在半导体器件中通常实现了用于产生水平排列的相变元件的焊盘。 如此定义的元件可以用在硫族化物存储单元或其他半导体器件中。

公开(公告)号：US06850432B2

公开(公告)日：2005-02-01

申请号：US10223975

申请日：2002-08-20

申请人： Chih-Yuan Lu ,  Yi-Chou Chen

发明人： Chih-Yuan Lu ,  Yi-Chou Chen

IPC分类号： G11C16/02 ,  G11C16/10 ,  G11C16/18 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/04 ,  G11C16/18 ,  G11C2213/72

摘要： Roughly described, a phase-change memory such as a chalcogenide-based memory is programmed optically and read electrically. No complex electrical circuits are required for programming the cells. On the other hand, this memory can be read by electrical circuitry directly. The read out speed is much faster than for optical disks, and integrated circuit chips made this way are more compatible with other electrical circuits than are optical disks. Thus memories according to the invention can have simple, low power-consuming, electrical circuits, and do not require slow and power-hungry disk drives for reading. The invention therefore provides a unique low power, fast read/write memory with simple electrical circuits.

摘要翻译： 粗略地描述，诸如基于硫族化物的存储器之类的相变存储器被光学地编程并且被电读取。 编程电池不需要复杂的电路。 另一方面，该存储器可以直接由电路读取。 读出速度比光盘快得多，而采用这种方式制成的集成电路芯片与其他电路比光盘更为兼容。 因此，根据本发明的存储器可以具有简单的，低功耗的电路，并且不需要用于读取的缓慢且耗电的磁盘驱动器。 因此，本发明提供了具有简单电路的独特的低功率，快速读/写存储器。

公开(公告)号：US10360552B2

公开(公告)日：2019-07-23

申请号：US14837601

申请日：2015-08-27

申请人： Yi-Chou Chen

发明人： Yi-Chou Chen

IPC分类号： G06Q20/10 ,  G06Q20/04 ,  G06Q20/32 ,  G06Q30/06

摘要： An implementing method of mobile group-buying system includes a buying group set-up step; a group-buying information creating step; a group-buying information transmitting step; and a group-buying information recording step. The mobile group-buying system is configured to allow at least two mobile communication devices to form a group-buying group, wherein each of the mobile communication devices is individually installed a group-buying APP. Further, initiator of each group-buying group can create group-buying information through the APP, and the group-buying information is issued to each participant of the buying group. Furthermore, when the buying group is established, the invitation of new attendants from any of the group participants to join the group of the same serial number is not accepted. Thus, the present disclosure not only can enhance participation rate of group-buying but also ensure the initiator and the participants in the buying group are in a first layer.

公开(公告)号：US20120181499A1

公开(公告)日：2012-07-19

申请号：US13046994

申请日：2011-03-14

申请人： Tung-Hua Chuang ,  Yi-Chou Chen ,  Tsung-Shune Chin ,  Kin-Fu Kao ,  Po-Chin Chang ,  Yung-Ching Chu

发明人： Tung-Hua Chuang ,  Yi-Chou Chen ,  Tsung-Shune Chin ,  Kin-Fu Kao ,  Po-Chin Chang ,  Yung-Ching Chu

IPC分类号： H01L45/00 ,  C09K3/00

CPC分类号： H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1625

摘要： A phase change material comprising a quaternary GaTeSb material consisting essentially of MA(GaxTeySbz)B, and where M comprises a group IVA element C, Si, Ge, Sn, Pb, a group VA element N, P, As, Sb, Bi, or a group VIA element O, S, Se, Te, Po, having a value A such that the transition temperature is increased relative to the transition temperature in GaxTeySbz, without M, and the difference between the melting temperature and the transition temperature is reduced relative to the difference in GaxTeySbz, without M.

摘要翻译： 一种相变材料，其包含基本上由MA（GaxTeySbz）B组成的四元GaTeSb材料，其中M包含IVA族元素C，Si，Ge，Sn，Pb，VA族元素N，P，As，Sb，Bi， 或具有值A的组VIA元素O，S，Se，Te，Po，使得转变温度相对于GaxTeySbz中的转变温度而不增加，并且熔融温度和转变温度之间的差减小 相对于GaxTeySbz的差异，没有M.

公开(公告)号：US08097871B2

公开(公告)日：2012-01-17

申请号：US12433573

申请日：2009-04-30

申请人： Shih-Hung Chen ,  Yi-Chou Chen

发明人： Shih-Hung Chen ,  Yi-Chou Chen

IPC分类号： H01L47/00

CPC分类号： H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675 ,  Y10S977/943

摘要： Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

摘要翻译： 与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。 结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。 因此，引起相变所需的电流量减少。

公开(公告)号：US08077505B2

公开(公告)日：2011-12-13

申请号：US12432055

申请日：2009-04-29

申请人： Yi-Chou Chen ,  Yuyu Lin

发明人： Yi-Chou Chen ,  Yuyu Lin

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.

摘要翻译： 这里描述了用于操作这样的设备的存储器件和方法。 本文所述的方法包括将复位偏置布置应用于存储单元，以将电阻状态从较低电阻状态改变到较高电阻状态。 复位偏置装置包括第一电压脉冲。 该方法还包括将设置偏置装置应用于存储单元，以将电阻状态从较高电阻状态改变到较低电阻状态。 所述设定偏置装置包括第二电压脉冲，所述第二电压脉冲的电压极性与所述第一电压脉冲的极性不同。