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公开(公告)号：US20110257953A1
公开(公告)日：2011-10-20
申请号：US12762848
申请日：2010-04-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。
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公开(公告)号：US08417752B1
公开(公告)日：2013-04-09
申请号：US12470254
申请日：2009-05-21
CPC分类号： H04B3/04
摘要： An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources. Further, in one implementation, each current source of the plurality of current sources includes a transistor and each set of control switches of the plurality of sets of control switches is for controlling a respective current source and includes a pair of transistors for controlling the respective current source.
摘要翻译： 描述了包括具有可编程电流源的均衡器级的均衡器电路。 在一个实现中，可编程电流源消除电压偏移。 而且，在一个实现中，可编程电流源可在用户模式下编程。 此外，在一个实现中，均衡器电路包括多个均衡器级，包括具有可编程电流源的均衡器级，其中具有可编程电流源的均衡器级是多个均衡器级中的第二均衡器级。 而且，在一个实现中，可编程电流源包括并联耦合的多个电流源和用于控制多个电流源的多组控制开关。 此外，在一个实现中，多个电流源的每个电流源包括晶体管，并且多组控制开关中的每组控制开关用于控制相应的电流源，并且包括用于控制相应电流的一对晶体管 资源。
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公开(公告)号：US07863941B1
公开(公告)日：2011-01-04
申请号：US12365585
申请日：2009-02-04
IPC分类号： H03K5/22
CPC分类号： H03K3/356139 , G11C7/065
摘要： A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.
摘要翻译： 电路包括在第一和第二输出节点处产生差分输出信号的差分电路。 电路还包括耦合到差分电路的第一输出节点的第一可变电容器和耦合到差分电路的第二输出节点的第二可变电容器。 响应于差分输出信号的测量，控制电路控制第一和第二可变电容器的电容。
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公开(公告)号：US08705602B1
公开(公告)日：2014-04-22
申请号：US12580587
申请日：2009-10-16
申请人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
CPC分类号： H04L25/03038 , H04L25/03343
摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
摘要翻译： 例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。 均衡器电路还包括多个电流数模转换器（“DAC”）。 均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各种DAC。 各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。
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公开(公告)号：US07245240B1
公开(公告)日：2007-07-17
申请号：US11370727
申请日：2006-03-07
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K5/15013
摘要： Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.
摘要翻译： 提供集成电路串行化器电路，其将并行数据转换为集成电路上的串行数据。 两相全局串行器主时钟发生器使用四相内部时钟来生成两相全局串行器主时钟。 两相全局串行器主时钟使用分布路径全局分布在集成电路上。 集成电路具有多个串行通信通道，每个通道具有相关联的串行器。 每个串行器包含从全局串行器主时钟的两个相位导出多个时钟信号的电路。 每个串行器使用派生时钟将并行数据转换为串行数据，以便通过其相关联的串行通信通道进行传输。 串行器每个都包含两个较小的串行器，它们将第一和第二组并行数据转换为第一和第二串行输出。 每个串行器中的2：1串行器合并第一个和第二个串行输出。
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公开(公告)号：US07557615B1
公开(公告)日：2009-07-07
申请号：US12069353
申请日：2008-02-08
申请人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
发明人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。 发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压， 和（6）电气空闲模式。
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公开(公告)号：US08391350B2
公开(公告)日：2013-03-05
申请号：US12875703
申请日：2010-09-03
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03636
摘要： Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.
摘要翻译： 判决反馈均衡器（DFE）电路用于确定在各种抽头中使用的系数，该误差信号的当前值的代数符号和DFE电路输出的先前的串行数据信号值。 使用这种代数符号信息（而不是全错误信号值）大大简化了确定抽头系数所需的电路。 DFE电路可以是自适应的，即，其自动调整抽头系数以改变串行数据信号传输条件。
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公开(公告)号：US20120057627A1
公开(公告)日：2012-03-08
申请号：US12875703
申请日：2010-09-03
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03636
摘要： Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.
摘要翻译： 判决反馈均衡器（“DFE”）电路基于在其各种抽头上使用的系数的确定，该误差信号的当前值的代数符号和DFE电路输出的先前串行数据信号值。 使用这种代数符号信息（而不是全错误信号值）大大简化了确定抽头系数所需的电路。 DFE电路可以是自适应的，即，其自动调整抽头系数以改变串行数据信号传输条件。
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49.发明授权公开(公告)号：US07482841B1
公开(公告)日：2009-01-27
申请号：US11731463
申请日：2007-03-29
申请人： Toan Thanh Nguyen , Thungoc M. Tran
发明人： Toan Thanh Nguyen , Thungoc M. Tran
IPC分类号： H03D13/00
CPC分类号： H03D13/004
摘要： Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.
摘要翻译： 提出了Bang-bang相位检测（BBPD）方法和电路，用于提供低延迟，低抖动相位检测，用于高数据速率应用。 BBPD方法和电路的缩短的数据路径实现提供了低延迟生成两个输出信号，包括输入信号的交替采样。 还提供组合逻辑电路以产生指示相对于时钟信号的输入信号的相位的时钟数据恢复（CDR）信号。 在整个BBPD定时电路中使用差分信号提供低抖动CDR信号的产生。
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公开(公告)号：US07777529B1
公开(公告)日：2010-08-17
申请号：US11269456
申请日：2005-11-07
申请人： Toan Thanh Nguyen , Thungoc M. Tran
发明人： Toan Thanh Nguyen , Thungoc M. Tran
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/412 , H03K19/0008
摘要： A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node voltage from rising and triggering an erroneous state change when a data signal changes in the middle of the clock cycle. The leakage compensation circuit associated with a node is activated when the node is set to a low logic level voltage. The leakage compensation circuit is adapted to draw a current from a node that compensates for the leakage current supplied to the node. At the least, this current draw is sufficient to prevent the voltage at the node from rising above a state change threshold voltage during the time period between refresh operations.
摘要翻译： 动态触发器包括允许在宽范围的频率上操作的漏电补偿电路。 动态触发器的节点存储触发器的状态。 当数据信号在时钟周期的中间改变时，泄漏补偿电路从这些节点漏出漏电流，以防止节点电压上升并触发错误状态改变。 当节点设置为低逻辑电平电压时，与节点相关联的漏电补偿电路被激活。 泄漏补偿电路适于从节点抽取电流来补偿提供给节点的漏电流。 至少，这种电流消耗足以防止在刷新操作期间节点处的电压升高到高于状态变化阈值电压。
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