-
公开(公告)号：US20230282279A1
公开(公告)日：2023-09-07
申请号：US17683356
申请日：2022-03-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Chia-Hung Lin , Jun-Yao Huang
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0007 , G11C2013/0045
Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether increasing rate of saturating read current is less than first threshold value; when increasing rate of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether increasing rate of saturating read current is less than first threshold value; finishing the method when increasing rate of saturating read current is less than first threshold value and saturating read current reaches target current value.
-
公开(公告)号：US20230038604A1
公开(公告)日：2023-02-09
申请号：US17960121
申请日：2022-10-04
Applicant: Winbond Electronics Corp.
Inventor： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
Abstract: A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.
-
公开(公告)号：US11176996B2
公开(公告)日：2021-11-16
申请号：US15930469
申请日：2020-05-13
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
-
公开(公告)号：US20210159275A1
公开(公告)日：2021-05-27
申请号：US16952085
申请日：2020-11-19
Applicant: Winbond Electronics Corp.
Inventor： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.
-
公开(公告)号：US11011231B2
公开(公告)日：2021-05-18
申请号：US16849976
申请日：2020-04-15
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
-
Patent Agency Ranking
公开(公告)号：US20210074356A1
公开(公告)日：2021-03-11
申请号：US16849976
申请日：2020-04-15
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
IPC: G11C13/00
Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
-
公开(公告)号：US20190035459A1
公开(公告)日：2019-01-31
申请号：US16045749
申请日：2018-07-26
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
-
公开(公告)号：US20190006007A1
公开(公告)日：2019-01-03
申请号：US15729676
申请日：2017-10-11
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
IPC: G11C13/00
Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.
-
公开(公告)号：US10170184B1
公开(公告)日：2019-01-01
申请号：US15729676
申请日：2017-10-11
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
IPC: G11C13/00
Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.
-
公开(公告)号：US10157962B2
公开(公告)日：2018-12-18
申请号：US14726626
申请日：2015-06-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao
Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.
-
-
-
-
-
-
-
-
-
Search Results
55
records
(took 0.019 seconds)
