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    PHYSICAL UNCLONABLE FUNCTION CODE GENERATING APPARATUS AND METHOD
    2.
    发明公开
    PHYSICAL UNCLONABLE FUNCTION CODE GENERATING APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20240333490A1

    公开(公告)日：2024-10-03

    申请号：US18587970

    申请日：2024-02-27

    Applicant: Winbond Electronics Corp.

    Inventor： Bo-Lun Wu ,  Po-Yen Hsu ,  Yi-Hsiu Chen

    IPC: H04L9/08

    CPC classification number: H04L9/0866

    Abstract: A physical unclonable function (PUF) code generating apparatus includes a PUF code generating element and a PUF code storage element. The PUF code generating element is configured to generate a PUF code. The PUF code storage element is coupled to the PUF code generating element. The PUF code storage element is configured to receive and store the PUF code. The PUF code generating element includes multiple first memory cells. Each of the first memory cells includes a gate layer, a semiconductor layer, and a tunnel oxide layer. The tunnel oxide layer is located between the gate layer and the semiconductor layer. The tunnel oxide layer includes a central area and a peripheral area. A ratio of a minimum thickness of the peripheral area to a maximum thickness of the central area of the tunnel oxide layer is defined as a corner ratio, and the corner ratio is less than 0.99.

    MANUFACTURING METHOD OF RESISTIVE RANDOM ACCESS MEMORY DEVICE
    3.
    发明申请
    MANUFACTURING METHOD OF RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20230038604A1

    公开(公告)日：2023-02-09

    申请号：US17960121

    申请日：2022-10-04

    Applicant: Winbond Electronics Corp.

    Inventor： Chia-Wen Cheng ,  Ping-Kun Wang ,  Yi-Hsiu Chen ,  He-Hsuan Chao

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210159275A1

    公开(公告)日：2021-05-27

    申请号：US16952085

    申请日：2020-11-19

    Applicant: Winbond Electronics Corp.

    Inventor： Chia-Wen Cheng ,  Ping-Kun Wang ,  Yi-Hsiu Chen ,  He-Hsuan Chao

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.

    Manufacturing method of resistive random access memory device
    7.
    发明授权
    Manufacturing method of resistive random access memory device 有权

    公开(公告)号：US12063796B2

    公开(公告)日：2024-08-13

    申请号：US17960121

    申请日：2022-10-04

    Applicant: Winbond Electronics Corp.

    Inventor： Chia-Wen Cheng ,  Ping-Kun Wang ,  Yi-Hsiu Chen ,  He-Hsuan Chao

    IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/84 ,  H10B63/30 ,  H10N70/061 ,  H10N70/841

    Abstract: A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.

    Resistive random access memory device and manufacturing method thereof
    8.
    发明授权
    Resistive random access memory device and manufacturing method thereof 有权

    公开(公告)号：US11502131B2

    公开(公告)日：2022-11-15

    申请号：US16952085

    申请日：2020-11-19

    Applicant: Winbond Electronics Corp.

    Inventor： Chia-Wen Cheng ,  Ping-Kun Wang ,  Yi-Hsiu Chen ,  He-Hsuan Chao

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.

    Resisitive random access memory structure and method for forming the same
    9.
    发明授权
    Resisitive random access memory structure and method for forming the same 有权

    公开(公告)号：US10950789B2

    公开(公告)日：2021-03-16

    申请号：US16428292

    申请日：2019-05-31

    Applicant: Winbond Electronics Corp.

    Inventor： Bo-Lun Wu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Po-Yen Hsu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.

    Resistive random access memory
    10.
    发明授权
    Resistive random access memory 有权

    公开(公告)号：US10593877B2

    公开(公告)日：2020-03-17

    申请号：US15949078

    申请日：2018-04-10

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Po-Yen Hsu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Bo-Lun Wu ,  Meng-Hung Lin ,  Chia-Hua Ho ,  Ming-Che Lin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

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