公开(公告)号：US08071621B2

公开(公告)日：2011-12-06

申请号：US12576319

申请日：2009-10-09

申请人： Thomas Simpson ,  James Kang ,  Jeffrey Albert ,  Cristobal Alhambra ,  Gerard Koether ,  James Woods ,  Yan Li

发明人： Thomas Simpson ,  James Kang ,  Jeffrey Albert ,  Cristobal Alhambra ,  Gerard Koether ,  James Woods ,  Yan Li

IPC分类号： C07D215/38 ,  A61K31/47 ,  A61P1/00 ,  A61P35/00 ,  A61P37/00 ,  A61P5/00 ,  A61P9/00

CPC分类号： C07D215/38 ,  C07D215/14 ,  C07D215/52

摘要： Compounds of Formula I wherein R1, A, R2, R3, R4, R5, R8, n, m, q and r are as described in the specification, pharmaceutically-acceptable salts, methods of making, pharmaceutical compositions containing and methods for using the same.

摘要翻译： 其中R 1，A，R 2，R 3，R 4，R 5，R 8，n，m，q和r如说明书中所述的式I化合物，药学上可接受的盐，制备方法，含药物组合物和使用方法 相同。

公开(公告)号：US20110235435A1

公开(公告)日：2011-09-29

申请号：US13154223

申请日：2011-06-06

申请人： Shou-Chang Tsao ,  Yan Li

发明人： Shou-Chang Tsao ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/3418 ,  G11C2211/5621

摘要： A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.

摘要翻译： 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件和省电技术具有降低检测期间的功耗的功能，包括在读取和编程/校验操作中 。 感测验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，在预充电操作期间，存储器单元与它们的位线的耦合被延迟，以便减小单元电流抵抗预充电工作。 在另一方面，通过在多遍感测操作中预先启动感测来使功耗预充电周期最小化。 作为过早感测的结果未检测到的高电流电池将在随后的通过中被检测到。

公开(公告)号：US20110222345A1

公开(公告)日：2011-09-15

申请号：US13114481

申请日：2011-05-24

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US08014209B2

公开(公告)日：2011-09-06

申请号：US12167135

申请日：2008-07-02

申请人： Jeffrey W Lutze ,  Yan Li

发明人： Jeffrey W Lutze ,  Yan Li

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

摘要： A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.

摘要翻译： 非易失性存储系统对多个非易失性存储元件执行编程，并且有选择地执行应该保持擦除的非易失性存储元件的至少一个子集的重新擦除，而无需有意地擦除编程数据。

公开(公告)号：US07974403B2

公开(公告)日：2011-07-05

申请号：US11505108

申请日：2006-08-15

申请人： Jun Wang ,  Yan Li ,  Yi Zhang ,  Jianfeng Liu

发明人： Jun Wang ,  Yan Li ,  Yi Zhang ,  Jianfeng Liu

IPC分类号： H04M1/00

CPC分类号： H04M3/4211 ,  H04M1/57 ,  H04M1/72519 ,  H04M3/42017 ,  H04M3/42059 ,  H04M3/42161 ,  H04M3/42382 ,  H04M3/436 ,  H04M2203/2011 ,  H04M2203/654

摘要： The present invention discloses a method for a called party to provide indication information for a calling party. The method includes the steps of: presetting the indication information to be provided to the calling party at the called party; before the called party answers the call in the connection procedure between the calling party and the called party, the network side obtaining the preset indication information from the called party and sending the indication information to the calling party. Accordingly, the present invention discloses a system for a called party to provide the indication information to a calling party. The present invention makes it possible that the called party flexibly selects the indication information to be provided to the calling party and the problem that only the indication information in the indication information database can be provided is avoided.

摘要翻译： 本发明公开了一种被叫方为主叫方提供指示信息的方法。 该方法包括以下步骤：在被叫方预置提供给主叫方的指示信息; 在被叫方在主叫方与被叫方之间的连接过程中应答呼叫时，网络侧从被叫方获取预设指示信息，并向主叫方发送指示信息。 因此，本发明公开了一种被叫方向主叫方提供指示信息的系统。 本发明使得被叫方能够灵活地选择要提供给主叫方的指示信息，并且避免了只能提供指示信息数据库中的指示信息的问题。

公开(公告)号：US20110141832A1

公开(公告)日：2011-06-16

申请号：US12638729

申请日：2009-12-15

申请人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

发明人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

IPC分类号： G11C11/416 ,  G11C7/10

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C13/0007 ,  G11C13/0061 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0076 ,  G11C2013/0085 ,  G11C2213/71

摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

摘要翻译： 非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。 在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。 不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。 一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

公开(公告)号：US20110141819A1

公开(公告)日：2011-06-16

申请号：US13035539

申请日：2011-02-25

申请人： Yan Li ,  Teruhiko Kamei ,  Jeffrey W. Lutze

发明人： Yan Li ,  Teruhiko Kamei ,  Jeffrey W. Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.

摘要翻译： 一组非易失性存储元件经受编程处理以便存储一组数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。 关于是继续编程还是编程成功的决定是基于非易失性存储元件的重叠组是否具有小于非正确编程的非易失性存储元件的阈值数量来进行。

公开(公告)号：US20110141818A1

公开(公告)日：2011-06-16

申请号：US13029787

申请日：2011-02-17

申请人： Yan Li

发明人： Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C8/10 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3454

摘要： Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.

摘要翻译： 由于存储在相邻的电荷存储元件中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的电荷存储元件上的视在电荷的变化。 为了补偿该耦合，给定存储器单元的编程过程可以考虑一个或多个相邻存储器单元的目标编程状态。 在每个编程脉冲之后验证编程量，编程单元的标准验证电平取决于目标状态。 验证级别进一步偏移较低，取决于相邻小区的扰动量，可由其目标状态确定。 验证级别优选地通过偏置相邻字线而不是实际上抵消标准验证电平而被虚拟地偏移。 对于软编程擦除的单元，考虑两个相邻字线上的相邻单元。

公开(公告)号：US07961706B2

公开(公告)日：2011-06-14

申请号：US12634147

申请日：2009-12-09

申请人： Shibi Huang ,  Peng Zhao ,  Yuxin Mao ,  Shiyong Tan ,  Weihua Wei ,  Yan Li

发明人： Shibi Huang ,  Peng Zhao ,  Yuxin Mao ,  Shiyong Tan ,  Weihua Wei ,  Yan Li

IPC分类号： H04J3/24

CPC分类号： H04W4/20 ,  H04L12/14 ,  H04L12/1428 ,  H04L12/1457 ,  H04L12/56 ,  H04L65/1016 ,  H04L65/80

摘要： A control method, system and function entity for reporting a bearer event of a signaling IP flow are provided. Flow identifier information such as a 5-tuple is generated for a signaling IP flow and a media IP flow so as to unify a mechanism for reporting a signaling path status and a mechanism for reporting a bearer event of a media IP flow, so that the mechanism for reporting a signaling path status is not limited by the parameter of Flow Usage, the PDP context with a signaling tag, thereby establishing corresponding PCC rules for signaling and the association between a signaling IP flow and a bearer. A method for reporting a signaling path status is further provided in the invention. In the method, for a default PDP context or a PDP context of a signaling IP flow, the predefined PCC rules are activated or signaling PCC rules generated in accordance with an Application Function address are installed, thereby an IP signaling path status is reported in accordance with rule names of the predefine PCC rules or the signaling PCC rules.

摘要翻译： 提供了用于报告信令IP流的承载事件的控制方法，系统和功能实体。 为信令IP流和媒体IP流生成诸如5元组的流标识符信息，以便统一用于报告信令路径状态的机制和用于报告媒体IP流的承载事件的机制，使得 用于报告信令路径状态的机制不受Flow Usage的参数，具有信令标签的PDP上下文的限制，从而建立用于信令的相应PCC规则以及信令IP流和承载之间的关联。 本发明还提供了一种报告信令路径状态的方法。 在该方法中，对于默认PDP上下文或信令IP流的PDP上下文，激活预定PCC规则或者安装根据应用功能地址生成的信令PCC规则，从而根据报告IP信令路径状态 具有预定义PCC规则或信令PCC规则的规则名称。

公开(公告)号：US20110122702A1

公开(公告)日：2011-05-26

申请号：US12624595

申请日：2009-11-24

申请人： Yan Li

发明人： Yan Li

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.

摘要翻译： 在存储元件的编程期间，补偿了沟道到浮置栅极耦合效应，以避免增加的编程速度和阈值电压分布加宽。 结合编程迭代，非选择的位线电压被升高以感应到选定位线的耦合，并且感测所选位线所经历的耦合量。 当施加编程脉冲时，基于耦合量设置所选位线的电压。 当检测到更多的耦合时，位线电压被设置得更高。 给定选定位线的耦合体验量是其与未选定位线的接近度的函数。 可以使用一个或多个耦合阈值来指示给定的所选位线分别具有一个或两个相邻的未选位线。