公开(公告)号：US20130210215A1

公开(公告)日：2013-08-15

申请号：US13396531

申请日：2012-02-14

申请人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

发明人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

摘要： A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

摘要翻译： 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US20140319601A1

公开(公告)日：2014-10-30

申请号：US13871144

申请日：2013-04-26

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

摘要翻译： 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US08785296B2

公开(公告)日：2014-07-22

申请号：US13396531

申请日：2012-02-14

申请人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

发明人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC分类号： H01L21/46 ,  H01L21/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

摘要： A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

摘要翻译： 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US08569169B2

公开(公告)日：2013-10-29

申请号：US13273219

申请日：2011-10-13

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC分类号： H01L21/44

CPC分类号： H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

摘要： A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

摘要翻译： 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US09136379B2

公开(公告)日：2015-09-15

申请号：US13871144

申请日：2013-04-26

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

摘要翻译： 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US20120248593A1

公开(公告)日：2012-10-04

申请号：US13494219

申请日：2012-06-12

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US08476752B2

公开(公告)日：2013-07-02

申请号：US13494219

申请日：2012-06-12

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US08436429B2

公开(公告)日：2013-05-07

申请号：US13118445

申请日：2011-05-29

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC分类号： H01L27/088

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

摘要翻译： 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US20140191334A1

公开(公告)日：2014-07-10

申请号：US13734201

申请日：2013-01-04

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC分类号： H01L23/495 ,  H01L27/088

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L27/088 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

摘要翻译： 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US08217503B2

公开(公告)日：2012-07-10

申请号：US12881372

申请日：2010-09-14

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。