公开(公告)号：US20090280611A1

公开(公告)日：2009-11-12

申请号：US12506993

申请日：2009-07-21

申请人： HANG-TING LUE ,  Erh-Kun Lai

发明人： HANG-TING LUE ,  Erh-Kun Lai

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L29/513

摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions. The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.

摘要翻译： 非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域 硅衬底在源区和漏区之间。 电池包括形成在基板的主表面上的底部氧化物层。 底部氧化物层设置在靠近阱区域的主表面的一部分上。 电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。 介电隧道层包括第一氧化物层，氮化物层和第二氧化物层。 擦除NVM单元包括施加正栅极电压以从栅极注入孔。

公开(公告)号：US20090096017A1

公开(公告)日：2009-04-16

申请号：US12337289

申请日：2008-12-17

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/4234

摘要： A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.

摘要翻译： 用于堆叠的非易失性存储器件的制造方法提供具有电荷俘获结构的多个位线层和字线层。 位线层具有形成在绝缘层上的多个位线，例如绝缘体上硅技术。 用相应的多个字线和与位线正交的电荷俘获结构对字线层进行构图。

公开(公告)号：US07511335B2

公开(公告)日：2009-03-31

申请号：US11429070

申请日：2006-05-05

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

摘要翻译： 提供非易失性存储器。 存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。 字线设置在基板上，与埋入位线交叉。

公开(公告)号：US20090065851A1

公开(公告)日：2009-03-12

申请号：US12267740

申请日：2008-11-10

申请人： Hang-Ting Lue ,  Erh-Kun Lai ,  Szu-Yu Wang

发明人： Hang-Ting Lue ,  Erh-Kun Lai ,  Szu-Yu Wang

IPC分类号： H01L29/792

CPC分类号： H01L29/42324 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513

摘要： A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN to tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.

摘要翻译： 非易失性存储器件包括具有半导体衬底，堆叠层的存储单元，以及设置在衬底的表面下方并由沟道区分隔开的源极和漏极区域的存储单元。 堆叠层包括设置在沟道区上的绝缘层，设置在绝缘层上的电荷存储层，电荷存储层上的多层隧道电介质结构，以及设置在多层隧道电介质结构上的栅极。 向栅极提供负偏压，通过多层隧道电介质结构通过-FN将电子注入电荷存储层，进行隧穿，使得器件的阈值电压增加。 向栅极提供正偏压，以通过+ FN隧穿通过多层隧道电介质结构将空穴注入电荷存储层，使得器件的阈值电压降低。

公开(公告)号：US20080175053A1

公开(公告)日：2008-07-24

申请号：US12056489

申请日：2008-03-27

申请人： Hang-Ting Lue ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

摘要： Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

摘要翻译： 存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。 单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

公开(公告)号：US20070134855A1

公开(公告)日：2007-06-14

申请号：US11425959

申请日：2006-06-22

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

摘要： A stacked non-volatile memory device comprises a plurality of bitline and word line layers stacked on top of each other. The bitline layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

摘要翻译： 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括可以使用先进的处理技术形成的多个位线，从而使设备的制造成本高效且成本有效。 该器件可以配置为NAND操作。

公开(公告)号：US20070029625A1

公开(公告)日：2007-02-08

申请号：US11197668

申请日：2005-08-04

申请人： Hang-Ting Lue ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L29/792 ,  H01L29/513

摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.

摘要翻译： 非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域 源极和漏极区域之间的硅衬底。该电池包括形成在衬底的主表面上的底部氧化物层。 底部氧化物层设置在靠近阱区域的主表面的一部分上。 电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。 电介质隧道层包括第一氧化物层，氮化物层和第二氧化物层。 擦除NVM单元包括施加正栅极电压以从栅极注入孔。

公开(公告)号：US08704205B2

公开(公告)日：2014-04-22

申请号：US13594353

申请日：2012-08-24

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

IPC分类号： H01L47/00

CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

公开(公告)号：US08481388B2

公开(公告)日：2013-07-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US08022489B2

公开(公告)日：2011-09-20

申请号：US11134155

申请日：2005-05-20

申请人： Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/788 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112

CPC分类号： H01L27/115 ,  G11C16/0408 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/515

摘要： An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.

摘要翻译： 空气隧道浮动栅极存储单元包括限定在衬底上的空气通道。 在空气隧道上定义第一多晶硅层（浮栅）。 氧化物层设置在第一多晶硅层上，使得氧化物层覆盖第一多晶硅层并限定空气通道的侧壁。 用作字线的第二多晶硅层被定义在氧化物层上。 还公开了一种制造空气通道浮动栅极存储单元的方法。 在衬底上形成牺牲层。 在牺牲层上形成第一多晶硅层。 在第一多晶硅层上沉积氧化物层，使得氧化物层覆盖第一多晶硅层并限定牺牲层的侧壁。 使用热磷酸（H 3 PO 4）浸渍来蚀刻掉牺牲层以形成空气通道。