公开(公告)号：US06587385B2

公开(公告)日：2003-07-01

申请号：US09843689

申请日：2001-04-30

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C700

CPC分类号： G11C11/4097 ,  G11C7/1072 ,  G11C2207/104

摘要： In successively executed operations modes in a synchronous semiconductor memory device, data access time after the application of a row access command is reduced by providing a plurality of control signal lines, such as a differential pair of sense amplifier enable lines, advantageously shorting the control lines, and then driving the control lines to a predetermined voltage level after the elapse of a prescribed time period.

摘要翻译： 在同步半导体存储器件中连续执行的操作模式中，通过提供多个控制信号线（例如差分对读出放大器使能线）来减少施加行存取命令之后的数据访问时间，有利地使控制线短路 ，然后在经过规定时间段之后将控制线驱动到预定的电压电平。

公开(公告)号：US06584005B1

公开(公告)日：2003-06-24

申请号：US10302963

申请日：2002-11-25

申请人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

发明人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

IPC分类号： G11C506

CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08

摘要： In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

摘要翻译： 在写入操作和读取操作中，基于存储器阵列中的所选存储单元列，将多个位线分成第一位线组和第二位线组。 第一位线组连接到第一和第二电压中的一个，并且第二位线组连接到另一个电压。 因此，当对应于所选择的存储单元的字线被激活时，所选存储单元行中未选择的存储单元的源极和漏极被设置为相同的电压电平。 因此，响应于字线的激活，不产生由每个位线的充电和放电产生的充电/放电电流。 这防止了对未选择的存储单元的错误写入和由于产生充电/放电电流引起的读取操作的延迟。

公开(公告)号：US06514834B2

公开(公告)日：2003-02-04

申请号：US09373604

申请日：1999-08-13

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： H01L2176

CPC分类号： H01L27/10808 ,  H01L27/10852

摘要： A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

摘要翻译： 在半导体基板的表面设有场氧化膜。 在半导体衬底上设置层间绝缘膜以覆盖有源层。 暴露活性层表面的接触孔设置在层间绝缘膜中。 导体填充接触孔以便电连接到有源层的表面。 场氧化膜的端部具有相对于半导体衬底的表面垂直的表面。 结果，可以获得改进的动态随机存取存储器，从而减少泄漏电流，这又增加了信息的保持时间。

公开(公告)号：US06480437B2

公开(公告)日：2002-11-12

申请号：US09986584

申请日：2001-11-09

申请人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C800

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/18

摘要： A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.

摘要翻译： 子放大器包括第一和第二晶体管，每个晶体管在每个栅极处接收子I / O线对的电位，第三晶体管由在存储器单元列方向上传输的信号控制，并且耦合第一和/ 第二晶体管和接地电位，以及由在存储单元行方向上传输的信号控制的第四和第五晶体管，并耦合第一和第二晶体管的漏极和主I / O线对。 由于子放大器由在列方向上发送的信号控制，所以可以减少与列选择信号的偏斜的影响。

公开(公告)号：US06442095B1

公开(公告)日：2002-08-27

申请号：US09692210

申请日：2000-10-20

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor memory device includes a logic unit, a DRAM unit, and first and second PMOS transistors In a normal mode, the first PMOS transistor is off and the second PMOS transistors is on, whereby power supply voltage is supplied to all the circuits. In a power down mode, the first PMOS transistor is on and the second PMOS transistor is off, so that power is not supplied to circuitry that is not required for a self refresh operation. Power supply voltage is provided to circuitry that is required for a self refresh operation. Thus, current consumption during self refresh can be reduced.

摘要翻译： 半导体存储器件包括逻辑单元，DRAM单元和第一和第二PMOS晶体管。在正常模式中，第一PMOS晶体管截止，第二PMOS晶体管导通，从而向所有电路提供电源电压。 在断电模式下，第一PMOS晶体管导通，第二PMOS晶体管截止，使得不向未自我刷新操作所需的电路提供电力。 电源电压被提供给自刷新操作所需的电路。 因此，可以减少自刷新期间的电流消耗。

公开(公告)号：US06441669B2

公开(公告)日：2002-08-27

申请号：US09797988

申请日：2001-03-05

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： H03L500

CPC分类号： G05F1/465

摘要： An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

摘要翻译： 公开了一种用于高精度地提供内部电源电位的内部电源电位电路。 外部电源电位（VCE）连接到具有用于向负载（11）施加内部电源电位（VCI）的漏极和接收控制信号（S1）的栅极的PMOS晶体管（Q1）的源极 ）从比较器（1）。 比较器（1）基于参考电位（Vref）和分压内部电源电位（DCI）之间的比较结果输出控制信号（S1）。 PMOS晶体管（Q1）的漏极连接到电阻器（R1）的第一端，电流源（2）连接在电阻器（R1）的第二端和地之间。 用作电阻器（R1）的第二端的节点（N1）处提供的电压作为分压的内部电源电位（DCI）施加到比较器（1）的正输入端。

公开(公告)号：US06429495B2

公开(公告)日：2002-08-06

申请号：US09208478

申请日：1998-12-10

申请人： Tsukasa Ooishi ,  Hiroki Shimano ,  Shigeki Tomishima

发明人： Tsukasa Ooishi ,  Hiroki Shimano ,  Shigeki Tomishima

IPC分类号： H01L2976

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L27/10897 ,  H01L29/66825 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

摘要翻译： 为了提供一种没有激光吹扫的地址编程装置，在半导体衬底上形成第一薄栅氧化膜，在其上形成第一栅电极，在其上形成第二厚栅极氧化膜，第二栅电极 形成在其上。 这种器件串联连接到相反极性的MOS晶体管，并且这种装置被交叉连接在一起以形成锁存电路。 要编程的数据及其反转版本被写入编程装置。 根据电源接通时锁存器的重量变化，读取编程信息。

公开(公告)号：US06421789B1

公开(公告)日：2002-07-16

申请号：US09333649

申请日：1999-06-16

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G06F1127

CPC分类号： G11C29/14 ,  G11C29/12015

摘要： A match detection circuit detecting match of data outputted to a plurality of data terminals is provided on an input/output circuit part. In a test, the same result is written in two latches, and alternately read in response to a clock signal. From a terminal outputting data at a double data rate in general, therefore, a test result can be outputted at a lower data rate. Observation is enabled with a tester having low performance, for reducing the cost for the test.

摘要翻译： 检测输出到多个数据端子的数据的匹配的匹配检测电路被提供在输入/输出电路部分上。 在测试中，相同的结果写入两个锁存器，并且响应于时钟信号交替地读取。 因此，从通常以双重数据速率输出数据的终端，可以以较低的数据速率输出测试结果。 使用具有低性能的测试仪进行观察，以降低测试成本。

公开(公告)号：US06414535B1

公开(公告)日：2002-07-02

申请号：US09525750

申请日：2000-03-14

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G05F302

CPC分类号： H03L7/10 ,  G06F1/10 ,  H03L7/0891 ,  H03L7/0995 ,  H04L7/033

摘要： A semiconductor memory device includes a difference adjusting circuit for detecting difference in at least one of phase and frequency between an external clock signal and an internal clock signal, for outputting a control potential for reducing the difference, and a current control circuit for adjusting driving current of an internal clock signal generating circuit in accordance with an output potential from the difference adjusting circuit. The current control circuit includes a current change restricting circuit for making smaller an amount of change of current in the clock signal generating circuit with respect to the change in the output potential from the difference adjusting circuit. An internal power supply voltage obtained by lowering internally the external power supply voltage is applied to the clock signal generating circuit. Further, when supply of the external clock signal is stopped, the output potential from the difference adjusting circuit is held. The internal power supply potential generating circuit further includes a current control circuit for adjusting an amount of current for supplying the internal power supply potential in accordance with the difference between an internal power supply potential and a prescribed potential level.

摘要翻译： 半导体存储器件包括：差分调整电路，用于检测外部时钟信号和内部时钟信号之间的相位和频率中的至少一个的差异，用于输出用于减小差的控制电位;以及电流控制电路，用于调节驱动电流 根据来自差分调整电路的输出电位的内部时钟信号发生电路。 电流控制电路包括电流变化限制电路，用于相对于来自差分调节电路的输出电位的变化使得时钟信号发生电路中的电流变化量变小。 通过将内部电源电压降低而获得的内部电源电压被施加到时钟信号发生电路。 此外，当外部时钟信号的供给停止时，来自差分调整电路的输出电位被保持。 内部电源电位发生电路还包括电流控制电路，用于根据内部电源电位和规定电位电平之间的差来调节用于提供内部电源电位的电流量。

公开(公告)号：US06384674B2

公开(公告)日：2002-05-07

申请号：US09353349

申请日：1999-07-15

申请人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

发明人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

IPC分类号： G05F110

CPC分类号： G11C5/063 ,  G11C11/4074 ,  G11C11/4097 ,  H02J1/06

摘要： Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.

摘要翻译： 提供了一种电源电源电容单元，包括连接在副电源线和副地线之间的第一电容器，连接在主电源线和副地线之间的第二电容器和连接在主电源线和副地线之间的第三电容器 在副电源线和主接地线之间。 因此，可以降低内部电路的电流消耗中的副电源线的电压降，使得内部电路的动作稳定，其运转速度提高。