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    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation
    3.
    发明授权
    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation 有权
    半导体存储器件防止写操作中的错误写入和读操作延迟

    公开(公告)号：US06584005B1

    公开(公告)日：2003-06-24

    申请号：US10302963

    申请日：2002-11-25

    申请人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    发明人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    IPC分类号： G11C506

    CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08

    摘要： In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

    摘要翻译： 在写入操作和读取操作中，基于存储器阵列中的所选存储单元列，将多个位线分成第一位线组和第二位线组。 第一位线组连接到第一和第二电压中的一个，并且第二位线组连接到另一个电压。 因此，当对应于所选择的存储单元的字线被激活时，所选存储单元行中未选择的存储单元的源极和漏极被设置为相同的电压电平。 因此，响应于字线的激活，不产生由每个位线的充电和放电产生的充电/放电电流。 这防止了对未选择的存储单元的错误写入和由于产生充电/放电电流引起的读取操作的延迟。

    Semiconductor memory device permitting improved integration density and reduced accessing time
    4.
    发明授权
    Semiconductor memory device permitting improved integration density and reduced accessing time 失效
    半导体存储器件允许改进的集成密度和减少的访问时间

    公开(公告)号：US06480437B2

    公开(公告)日：2002-11-12

    申请号：US09986584

    申请日：2001-11-09

    申请人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

    发明人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

    IPC分类号： G11C800

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/18

    摘要： A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.

    摘要翻译： 子放大器包括第一和第二晶体管，每个晶体管在每个栅极处接收子I / O线对的电位，第三晶体管由在存储器单元列方向上传输的信号控制，并且耦合第一和/ 第二晶体管和接地电位，以及由在存储单元行方向上传输的信号控制的第四和第五晶体管，并耦合第一和第二晶体管的漏极和主I / O线对。 由于子放大器由在列方向上发送的信号控制，所以可以减少与列选择信号的偏斜的影响。

    Semiconductor memory device permitting improved integration density and reduced accessing time
    5.
    发明授权
    Semiconductor memory device permitting improved integration density and reduced accessing time 失效
    半导体存储器件允许改进的集成密度和减少的访问时间

    公开(公告)号：US06333884B1

    公开(公告)日：2001-12-25

    申请号：US09311560

    申请日：1999-05-14

    申请人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

    发明人： Hiroshi Kato ,  Tsukasa Ooishi ,  Hideto Hidaka

    IPC分类号： G11C702

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/18

    摘要： A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.

    摘要翻译： 子放大器包括第一和第二晶体管，每个晶体管在每个栅极处接收子I / O线对的电位，第三晶体管由在存储器单元列方向上传输的信号控制，并且耦合第一和/ 第二晶体管和接地电位，以及由在存储单元行方向上传输的信号控制的第四和第五晶体管，并耦合第一和第二晶体管的漏极和主I / O线对。 由于子放大器由在列方向上发送的信号控制，所以可以减少与列选择信号的偏斜的影响。