公开(公告)号：US07007138B2

公开(公告)日：2006-02-28

申请号：US10413758

申请日：2003-04-15

申请人： Tetsuji Mochida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

发明人： Tetsuji Mochida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

IPC分类号： G06F13/16

CPC分类号： G06F13/1642

摘要： In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

摘要翻译： 在根据本发明的资源请求仲裁设备中，请求屏蔽单元以资源请求设备所需的最小频率对由资源请求设备发出的存储器访问请求REQ进行掩码，并且仲裁单元确认 基于优先级的预定静态顺序，请求屏蔽单元未暂停的存储器访问请求RREQ。 在该资源请求仲裁装置中，仲裁单元不需要涉及存储器访问请求单元之间的预定优先级顺序以外的任何其他事项，并且基于静态优先级顺序的容易且简单的仲裁系统确保用于确认资源的最小频率 请求每个存储器访问请求单元需要。

公开(公告)号：US08260075B2

公开(公告)日：2012-09-04

申请号：US12097994

申请日：2006-11-21

申请人： Akihiko Inoue ,  Tokuzo Kiyohara

发明人： Akihiko Inoue ,  Tokuzo Kiyohara

IPC分类号： G06K9/00

CPC分类号： G06T3/4007 ,  G06T2200/28 ,  H04N19/82

摘要： A two-dimensional filter arithmetic device comprises a picture memory, a line memory, a vertical filtering unit which includes nine first filter modules installed in parallel, a buffer for timing adjustments, and a horizontal filtering unit which includes four second filter modules installed in parallel. From the line memory, the pixel values of nine full pels per line are inputted in parallel to the vertical filtering unit, nine vertically-filtered values of half pels are generated and inputted to the horizontal filtering unit; thereby, four two-dimensionally-filtered values of half pels are generated.

摘要翻译： 二维滤波器运算装置包括图像存储器，行存储器，垂直滤波单元，其包括并联安装的九个第一滤波器模块，用于定时调整的缓冲器和包括并联安装的四个第二滤波器模块的水平滤波单元 。 从行存储器中，与垂直滤波单元并行地输入每行9个全像素的像素值，生成半个像素的九个垂直滤波值并输入到水平滤波单元; 从而产生半个像素的四维二维滤波值。

公开(公告)号：US07926055B2

公开(公告)日：2011-04-12

申请号：US11574359

申请日：2006-04-12

申请人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

发明人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

IPC分类号： G06F9/46

CPC分类号： G06F15/7867 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.

摘要翻译： 本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。 处理器存储分别对应于多个线程的电路配置信息集合，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程 设置对应于线程。 在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

公开(公告)号：US20070286275A1

公开(公告)日：2007-12-13

申请号：US10599494

申请日：2005-04-01

申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

IPC分类号： H04B1/66 ,  G06F13/12

CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

摘要： The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.

摘要翻译： 本发明提供了一种用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 该集成电路包括一个包括CPU的微处理器块2，用于向外部设备输入/输出视频和音频流的流I / O块4，用于执行媒体处理的媒体处理块3，包括至少一个 输入到流I / O块4的视频和音频流等的压缩和解压缩，用于将经过媒体处理块3中的媒体处理的视频和音频流转换成视频和音频信号的AV IO块5 并将这些信号输出到外部设备等;以及存储器IF块6，用于控制微计算机块2，流I / C块4，媒体处理块3和AV IO块5之间的数据传输，以及外部 记忆9。

公开(公告)号：US20070028055A1

公开(公告)日：2007-02-01

申请号：US10571531

申请日：2004-08-23

申请人： Tetsuya Tanaka ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Keishi Chikamura

发明人： Tetsuya Tanaka ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Keishi Chikamura

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/124

摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.

摘要翻译： 本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

公开(公告)号：US5469552A

公开(公告)日：1995-11-21

申请号：US310627

申请日：1994-09-22

申请人： Masato Suzuki ,  Tokuzo Kiyohara

发明人： Masato Suzuki ,  Tokuzo Kiyohara

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3867

摘要： A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch control data regarding operand fetching and operation control data regarding execution of the instruction; an execution unit for receiving the execution control data directly from the instruction decode unit, and executing a predetermined operation based on the operation control data; and an operand fetch unit for receiving the fetch control data directly from the instruction decode unit, and fetching an operand from a source other than registers in the execution unit. The operand fetch unit fetches the operand concurrently with processing in a second cycle, and subsequent cycles if any, of the operation executed by the execution unit and requiring at least two machine cycles for execution.

摘要翻译： 具有流水线架构的数据处理装置包括用于从存储器取出指令的指令提取单元; 指令解码单元，用于对由指令获取单元取出的指令进行解码，并且输出关于操作数获取的读取控制数据和关于指令执行的操作控制数据; 执行单元，用于直接从指令解码单元接收执行控制数据，并且基于操作控制数据执行预定操作; 以及操作数取出单元，用于直接从指令解码单元接收取出控制数据，以及从除执行单元中的寄存器之外的源取得操作数。 操作数提取单元在第二个周期中与处理并行执行操作数，以及执行单元执行的操作的后续周期，并且需要至少两个机器周期执行。

公开(公告)号：US09189989B2

公开(公告)日：2015-11-17

申请号：US13393349

申请日：2011-06-09

申请人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

发明人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

IPC分类号： G09G3/28 ,  G09G3/288 ,  G09G3/293 ,  G09G3/20 ,  G09G5/395

CPC分类号： G09G3/288 ,  G09G3/2022 ,  G09G3/293 ,  G09G5/395 ,  G09G2320/103

摘要： A plasma display system restricts peak data traffic when a shared memory is used. In the plasma display system, a control unit prohibits a moving picture decoder from accessing a shared memory while an SF reading unit is reading, from the shared memory, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit permits the moving picture decoder to access the shared memory while the SF reading unit is not reading the SF pixel data from the shared memory during a sustain discharge period.

摘要翻译： 当使用共享存储器时，等离子体显示系统限制峰值数据流量。 在等离子体显示系统中，控制单元在SF读取单元正在从共享存储器读取作为多个子场中要照明的单元的信息的SF像素数据时，禁止运动图像解码器访问共享存储器。 另一方面，控制单元允许运动图像解码器访问共享存储器，而SF读取单元在维持放电期间未从共享存储器读取SF像素数据。

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。

公开(公告)号：US5511172A

公开(公告)日：1996-04-23

申请号：US977238

申请日：1992-11-16

申请人： Kozo Kimura ,  Kosuki Yoshioka ,  Tokuzo Kiyohara

发明人： Kozo Kimura ,  Kosuki Yoshioka ,  Tokuzo Kiyohara

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/3842

摘要： The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory. The processor comprises an instruction type distinguishing device for distinguishing a type of a conditional branch instruction included in the unexecuted instruction sequence, the condition of the conditional branch instruction depending on another instruction, an instruction parallel-issuing device for issuing in parallel instructions included in a succeeding instruction sequence to be executed following the conditional branch instruction and/or instructions included in an instruction sequence to be executed after the branching to the executing units while whether or not to branch is not determined, a branching determining device for determining whether to branch when the another instruction is executed, and an execution result managing device for identifying whether the execution results of the instruction sequences are effective based on the determining results of the branching determining device.

摘要翻译： 本发明公开了一种推测执行处理器，包括多个执行单元，用于并行处理存储在其存储器中的指令序列中的多个指令。 处理器包括：指令类型识别装置，用于区分未执行指令序列中包括的条件转移指令的类型，根据另一指令执行条件转移指令的条件;并行指令发行装置， 在分支到执行单元之后执行的条件分支指令和/或包括在执行单元之后执行的指令执行的后续指令序列，而不确定是否分支;分支确定装置，用于确定是否分支 执行另一指令，以及执行结果管理装置，用于基于分支确定装置的确定结果来识别指令序列的执行结果是否有效。

公开(公告)号：US5210849A

公开(公告)日：1993-05-11

申请号：US539910

申请日：1990-06-18

申请人： Kazunori Takahashi ,  Tokuzo Kiyohara

发明人： Kazunori Takahashi ,  Tokuzo Kiyohara

IPC分类号： G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0851 ,  G06F12/0864

摘要： In a cache memory simultaneously conducting updating for a miss and a decision on a miss for the subsequent address, a write flag generated by a control unit is written in a valid flag field. Based on this operation, during an access to an external memory at an occurrence of a miss, a tag field and the valid flag field are simultaneously updated. When updating a data field, a read operation is achieved on the tag and valid flag fields to decide occurrence of miss. Thus, an external memory access for a miss at a next address can be executed at an earlier point of time. Moreover, by the provision of a data latch disposed for an output from the data field, and by reading data at a next address and keeping it in the data latch during a memory read cycle, succeeding hit data can be outputted immediately after a miss processing is completed. Furthermore, also in a cache memory having a plurality of tag fields and a plurality of valid flag fields, the updating for a miss and the decision on a miss for a next address can be attained at the same time.