公开(公告)号：US08035146B2

公开(公告)日：2011-10-11

申请号：US12820092

申请日：2010-06-21

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

摘要翻译： 非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。 根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

公开(公告)号：US20110187429A1

公开(公告)日：2011-08-04

申请号：US12838332

申请日：2010-07-16

申请人： Sang Jin BYEON ,  Jae Jin Lee

发明人： Sang Jin BYEON ,  Jae Jin Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/00

摘要： A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

摘要翻译： 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US07741668B2

公开(公告)日：2010-06-22

申请号：US11717081

申请日：2007-03-13

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

摘要翻译： 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，并且在绝缘层上形成包括N型漏极区，P型沟道区和N型源极区的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US20100090780A1

公开(公告)日：2010-04-15

申请号：US12588432

申请日：2009-10-15

申请人： In Sang Song ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun ,  Jae Jin Lee ,  Seong Jun Cho

发明人： In Sang Song ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun ,  Jae Jin Lee ,  Seong Jun Cho

IPC分类号： H01P1/18

CPC分类号： H01P1/184

摘要： A phase shifter includes a substrate; a signal line formed on a specific region in an upper surface of the substrate; and an air gap which is formed within the substrate and changes effective permittivity of the substrate to delay phase of a signal supplied to the signal line. The phase shifter delays a phase of a signal by controlling effective permittivity using an air gap, thereby having outstandingly low insertion loss as compared to existing phase shifters. Further, the phase shifter can be manufactured in a same length as a reference line so that the phase shifter can be in a compact size.

摘要翻译： 移相器包括基板; 形成在所述基板的上表面的特定区域上的信号线; 以及形成在衬底内的气隙，并且改变衬底的有效介电常数以延迟提供给信号线的信号的相位。 移相器通过使用气隙控制有效介电常数来延迟信号的相位，从而与现有的移相器相比具有非常低的插入损耗。 此外，移相器可以制造成与参考线相同的长度，使得移相器可以是紧凑的尺寸。

公开(公告)号：US07646318B2

公开(公告)日：2010-01-12

申请号：US12181769

申请日：2008-07-29

申请人： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

发明人： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

IPC分类号： H03M7/00

CPC分类号： H04N19/42 ,  H04N19/44 ,  H04N19/91

摘要： Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

摘要翻译： 提供了一种基于应用特定指令集处理器（ASIP）的H.264上下文自适应可变长度编码（CAVLC）解码方法。 H.264 CAVLC解码方法包括：基于解码系数的表确定多个比较比特串，将比较比特列的长度存储在第一寄存器中，将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串，并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数，而不访问存储器，并且防止由存储器访问引起的速度降低，从而提高H.264解码器的解码速度。

公开(公告)号：US07126411B2

公开(公告)日：2006-10-24

申请号：US10999593

申请日：2004-11-30

申请人： Ji Eun Jang ,  Jae Jin Lee

发明人： Ji Eun Jang ,  Jae Jin Lee

IPC分类号： G05F1/10

CPC分类号： H03K17/302 ,  G11C5/145 ,  H02M3/07

摘要： Disclosed is a high voltage generator comprising: a first voltage level detector for detecting a voltage level of the high voltage; a second voltage level detector for detecting difference between the high voltage and a power supply voltage; a high voltage pump for performing a pumping operation to generate a high voltage when one of output signals of the first voltage level detector and the second voltage level detector is enabled; and a controller for receiving the output signal of the second voltage level detector, and for connecting a terminal through which the high voltage is output with the power supply voltage when the high voltage is lower than the power supply voltage.

公开(公告)号：US06885605B2

公开(公告)日：2005-04-26

申请号：US10255999

申请日：2002-09-26

申请人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

发明人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

IPC分类号： H03K19/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4193

CPC分类号： G11C11/4074 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2227

摘要： A power-up signal generator uses a deep power down power-up signal, which should be in a standby state in a deep power down entry, for an initialization of other semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal, a deep power down power-up signal generator for generating a deep power down power-up signal, a power-up signal generator for generating a power-up signal and a power-up controller for determining whether or not to enable the power-up signal in the deep power down entry.

摘要翻译： 上电信号发生器使用深度掉电加电信号，其将处于深功率下降条目中的待机状态，用于在内部电源电压为内部操作的DRAM器件中的其它半导体元件的初始化 生成。 发电机还使用上电信号，该信号在深度掉电输入中被禁用，并通过内部电源电压在深度断电输出中使能。 该发生器可以包括用于产生上电检测信号的上电检测器，用于产生深度掉电上电信号的深度断电上电信号发生器，用于产生上电的上电信号发生器 信号和上电控制器，用于确定是否在深度断电输入中启用上电信号。

公开(公告)号：US06765406B2

公开(公告)日：2004-07-20

申请号：US10330821

申请日：2002-12-27

申请人： Ji Eun Jang ,  Jae Jin Lee

发明人： Ji Eun Jang ,  Jae Jin Lee

IPC分类号： H03K19003

CPC分类号： H05K1/0246 ,  G11C7/10 ,  G11C11/4093 ,  H03K19/0175 ,  H05K1/0286 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022

摘要： A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.

摘要翻译： 公开了一种被配置为提供多个接口的电路板。 电路板包括插入有终端模块的终端插槽，其配置成通过施加终端电阻和终止电压来调制电路。 如果终端模块插入终端插槽，则电路板作为串行存根终端收发器逻辑（SSTL）接口运行。 否则，该板作为低电压晶体管逻辑（LVTTL）接口工作。 另外，电路板包括被配置为选择性地将终端电阻连接到总线的开关。 如果开关将终端电阻连接到总线，则该板作为SSTL接口工作。 否则，该板作为LVTTL接口运行。

公开(公告)号：US06759280B2

公开(公告)日：2004-07-06

申请号：US10246834

申请日：2002-09-18

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： H01L2182

CPC分类号： H01L27/10897 ,  G11C11/4097 ,  H01L27/10885

摘要： The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.

摘要翻译： 本发明涉及具有分立位线，共享读出放大器结构的改进的存储电路。 在传统的分割位线，共享读出放大器配置中，两个相邻存储器子阵列通常位于两组读出放大器之间，并且两个相邻存储器子阵列的选定位线通常连接到具有金属触点的金属线 降低容性负载。 在本发明中，来自读出放大器的任意一组的一些读出放大器被重新定位到两个相邻存储器子阵列之间的区域，从而允许重新定位的读出放大器被共享。 结果，任何两个相邻的存储器子阵列共享一组读出放大器。 此外，来自两个相邻的存储器子阵列的选定的位线被耦合到重新定位的读出放大器内的金属线。 此外，平衡电路类似地重新定位到两个相邻的存储器子阵列之间的区域，从而允许在更短的时间段内对所选择的位线和金属线进行预充电和均衡。 通过减少预充电时间，可以实现更快的存储器访问。

公开(公告)号：US06479851B1

公开(公告)日：2002-11-12

申请号：US09573070

申请日：2000-05-16

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： H01L27108

CPC分类号： H01L27/10897 ,  G11C11/4097 ,  H01L27/10885

摘要： The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.

摘要翻译： 本发明涉及具有分立位线，共享读出放大器结构的改进的存储电路。 在传统的分割位线，共享读出放大器配置中，两个相邻存储器子阵列通常位于两组读出放大器之间，并且两个相邻存储器子阵列的选定位线通常连接到具有金属触点的金属线 降低容性负载。 在本发明中，来自读出放大器的任意一组的一些读出放大器被重新定位到两个相邻存储器子阵列之间的区域，从而允许重新定位的读出放大器被共享。 结果，任何两个相邻的存储器子阵列共享一组读出放大器。 此外，来自两个相邻存储器子阵列的选定位线耦合到重定位的读出放大器内的金属线。 此外，平衡电路类似地重新定位到两个相邻的存储器子阵列之间的区域，从而允许在更短的时间段内对所选择的位线和金属线进行预充电和均衡。 通过减少预充电时间，可以实现更快的存储器访问。