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83 条记录 (耗时 0.036 秒)

    INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
    42.
    发明申请
    INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL 有权
    集成电路，包括可编程逻辑和外部器件芯片允许超控

    公开(公告)号：US20080048716A1

    公开(公告)日：2008-02-28

    申请号：US11932901

    申请日：2007-10-31

    申请人： Rabindranath Balasubramanian ,  Kurt Kolkind ,  Gregory Bakker

    发明人： Rabindranath Balasubramanian ,  Kurt Kolkind ,  Gregory Bakker

    IPC分类号： H03K19/173

    CPC分类号： G06F1/30 ,  G06F1/08 ,  G06F1/24 ,  G06F1/28 ,  H03K19/17744

    摘要： An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

    摘要翻译： 集成电路装置包括可编程逻辑块，监视输入，条件感测电路，耦合到所述监控输入并且被配置为响应于感测所述监视输入处的状况而在输出处产生状态感测信号，第一数字 输入，第一数字输出和门控电路，其配置在可编程逻辑块中并耦合在第一数字输入和第一数字输出之间。 门控电路具有耦合到条件感测电路并且产生输出的选通输入。 在不存在条件感测信号的情况下，该输出与第一数字输入的输入状态相关，并且在条件感测信号存在的情况下采用超驰状态。

    FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY
    44.
    发明申请
    FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY 有权
    闪存/动态随机存取现场可编程门阵列

    公开(公告)号：US20070104009A1

    公开(公告)日：2007-05-10

    申请号：US11619547

    申请日：2007-01-03

    申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

    发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

    IPC分类号： G11C7/00

    CPC分类号： G11C11/404 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4093 ,  G11C14/00 ,  G11C14/0018 ,  G11C16/0441 ,  G11C16/3431

    摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

    摘要翻译： 用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。 刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。 开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。 地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

    NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
    45.
    发明申请
    NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
    FPGA的非易失性查看表

    公开(公告)号：US20070047330A1

    公开(公告)日：2007-03-01

    申请号：US11551973

    申请日：2006-10-23

    申请人： John McCollum ,  Gregory Bakker ,  Jonathan Greene

    发明人： John McCollum ,  Gregory Bakker ,  Jonathan Greene

    IPC分类号： G11C7/10

    CPC分类号： H03K19/17728

    摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

    摘要翻译： 用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。 非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。 如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。 多路复用器的输出通过上拉晶体管耦合到V CC。 上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。 读出放大器耦合到多路复用器的输出端。

    Non-volatile look-up table for an FPGA
    46.
    发明授权
    Non-volatile look-up table for an FPGA 有权
    FPGA的非易失性查找表

    公开(公告)号：US07129748B1

    公开(公告)日：2006-10-31

    申请号：US11026336

    申请日：2004-12-29

    申请人： John McCollum ,  Gregory Bakker ,  Jonathan Greene

    发明人： John McCollum ,  Gregory Bakker ,  Jonathan Greene

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728

    摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

    摘要翻译： 用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。 非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。 如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。 多路复用器的输出通过上拉晶体管耦合到V CC。 上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。 读出放大器耦合到多路复用器的输出端。

    ESD protection structure for I/O pad subject to both positive and negative voltages
    48.
    发明授权
    ESD protection structure for I/O pad subject to both positive and negative voltages 有权
    I / O焊盘的ESD保护结构受到正和负电压的影响

    公开(公告)号：US07659585B2

    公开(公告)日：2010-02-09

    申请号：US12179243

    申请日：2008-07-24

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.

    摘要翻译： 公开了一种ESD保护电路，用于形成在三阱工艺的内部p阱中的n沟道MOS晶体管，并连接到根据本发明可以经历正和负电压的I / O焊盘。 如果I / O焊盘的电压为正，则第一开关将包含n沟道MOS晶体管的p阱连接到地，而第二开关将包含n沟道MOS晶体管的p阱连接到I / O焊盘 如果I / O焊盘的电压为负。 第三开关将n沟道MOS晶体管的栅极连接到p阱，如果它被截止，并且第四开关将n沟道MOS晶体管的栅极连接到Vcc，如果它是导通的。