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    METHOD AND APPARATUS FOR MANAGING MEMORY
    41.
    发明公开
    METHOD AND APPARATUS FOR MANAGING MEMORY 审中-公开

    公开(公告)号：US20240201876A1

    公开(公告)日：2024-06-20

    申请号：US18083306

    申请日：2022-12-16

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673

    Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

    Accelerated frame transmission
    42.
    发明授权
    Accelerated frame transmission 有权

    公开(公告)号：US12014700B2

    公开(公告)日：2024-06-18

    申请号：US18089837

    申请日：2022-12-28

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Syed Athar Hussain ,  Anthony W L Koo ,  David I. J. Glen

    IPC: G09G5/12 ,  G06T1/20 ,  G06T9/00 ,  G09G5/00

    CPC classification number: G09G5/00 ,  G06T1/20 ,  G06T9/00 ,  G09G2330/023 ,  G09G2360/18 ,  G09G2370/12

    Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

    PLANE-BASED SCREEN CAPTURE
    43.
    发明公开
    PLANE-BASED SCREEN CAPTURE 审中-公开

    公开(公告)号：US20240194166A1

    公开(公告)日：2024-06-13

    申请号：US18080173

    申请日：2022-12-13

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Yuping Shen ,  Min Zhang

    IPC: G09G5/14 ,  G09G5/36 ,  H04L67/1095

    CPC classification number: G09G5/14 ,  G09G5/363 ,  H04L67/1095 ,  G09G2340/12 ,  G09G2370/022

    Abstract: A request is received from an application to present content generated by the application in an overlay plane of a multi-plane display system. Responsive to determining that current system resources support presentation of the generated content in the overlay plane, frames of the generated content are displayed in the overlay plane and captured directly from the overlay plane such that the captured frames may be provided to one or more remote client computing systems independently of frames captured from one or more additional overlay planes and from an underlying composited desktop layer. Identifiers of prioritized applications may be maintained based on user preferences to determine specific applications for which generated content is enabled for display via overlay plane.

    SRAM COLUMN SLEEP CIRCUITS FOR LEAKAGE SAVINGS WITH RAPID WAKE
    44.
    发明公开
    SRAM COLUMN SLEEP CIRCUITS FOR LEAKAGE SAVINGS WITH RAPID WAKE 审中-公开

    公开(公告)号：US20240176514A1

    公开(公告)日：2024-05-30

    申请号：US18059360

    申请日：2022-11-28

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Sahilpreet Singh ,  Peter Louiz Rezk Beshay ,  Russell Schreiber

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0673

    Abstract: An apparatus and method for efficiently designing memory arrays in semiconductor dies. In various implementations, a memory array utilizes wake pre-charge circuitry to reduce both leakage current and a transition from an idle state. When control circuitry of the memory array determines that there are no upcoming memory accesses, it disables bit line pre-charge circuitry of columns of the array. The control circuitry enables wake pre-charge circuitry to charge the bit lines to an idle voltage level equal to a difference between the power supply voltage level and a threshold voltage of a transistor. When the control circuitry determines a memory access is pending, the control circuitry transitions the memory array to an active state. Both the amount of voltage difference and the resulting latency to charge the bit lines from the idle voltage level to the power supply reference voltage level are small.

    AVOID REDUCED EFFECTIVE BANDWIDTH ON TRANSMISSION LINES IN THE PRESENCE OF CLOCK DOMAIN DIFFERENCES
    45.
    发明公开
    AVOID REDUCED EFFECTIVE BANDWIDTH ON TRANSMISSION LINES IN THE PRESENCE OF CLOCK DOMAIN DIFFERENCES 审中-公开

    公开(公告)号：US20240168515A1

    公开(公告)日：2024-05-23

    申请号：US18057710

    申请日：2022-11-21

    Applicant: ATI Technologies ULC

    Inventor： Yanfeng Wang ,  Shaofeng An

    IPC: G06F1/12 ,  G06F1/08

    CPC classification number: G06F1/12 ,  G06F1/08

    Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

    Granular clock frequency division using dithering mechanism
    49.
    发明授权
    Granular clock frequency division using dithering mechanism 有权

    公开(公告)号：US11955982B2

    公开(公告)日：2024-04-09

    申请号：US17853323

    申请日：2022-06-29

    Applicant: ATI Technologies ULC

    Inventor： Erwin Chi Wang Pang

    IPC: H03L7/197 ,  H03L7/08 ,  H03L7/081

    CPC classification number: H03L7/1974 ,  H03L7/0805 ,  H03L7/0816

    Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

    Real-time GPU rendering with performance guaranteed power management
    50.
    发明授权
    Real-time GPU rendering with performance guaranteed power management 有权

    公开(公告)号：US11954792B2

    公开(公告)日：2024-04-09

    申请号：US17408034

    申请日：2021-08-20

    Applicant: ATI Technologies ULC

    Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Clarence Ip ,  Tung Chuen Kwong

    IPC: G06T15/20 ,  G06F15/78 ,  G06T1/20 ,  G09G5/14

    CPC classification number: G06T15/205 ,  G06F15/7814 ,  G06T1/20 ,  G09G5/14 ,  G09G2320/0261

    Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.

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