公开(公告)号：US5815037A

公开(公告)日：1998-09-29

申请号：US651106

申请日：1996-05-21

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Ivan Bietti ,  Giancarlo Clerici

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Ivan Bietti ,  Giancarlo Clerici

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45982 ,  H03F2203/45526

Abstract: A high-pass filter includes at least one circuit unit constituted by a first branch and a second branch both connected to an input of the filter on one side and, on the other side, to an adder the output of which is the output of the filter. The first branch includes means for transferring an input signal substantially without modifying its frequency content, and the second branch comprises a low-pass filter. The circuit elements are chosen such that the components of the input signal with frequencies below the cut-off frequency of the low-pass filter are substantially cancelled out at the output of the adder. The filter is suitable for being produced within a particularly small area in an integrated circuit.

Abstract translation: 高通滤波器包括由一侧连接到滤波器的输入的第一分支和第二分支构成的至少一个电路单元，另一侧由加法器输出，该加法器的输出为 过滤。 第一分支包括用于基本上不修改其频率内容来传送输入信号的装置，并且第二分支包括低通滤波器。 电路元件被选择为使得低于低通滤波器的截止频率的输入信号的分量在加法器的输出处基本抵消。 该滤波器适合于在集成电路的特别小的区域内产生。

公开(公告)号：US5808488A

公开(公告)日：1998-09-15

申请号：US755466

申请日：1996-11-22

Applicant: Melchiorre Bruccoleri ,  Paolo Cusinato

Inventor： Melchiorre Bruccoleri ,  Paolo Cusinato

IPC: H03K3/037 ,  H03K3/356 ,  H03K5/153

CPC classification number: H03K3/356156

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract translation: 描述了一种定时双稳态电路，其包括两个逆变器，每个逆变器的输入连接到另一个的输出，经由“缓冲器”的输出和电路的输入经由受控的电子开关。 逆变器的电源端子通过另外两个受控开关连接到电路的电源端子。 时钟发生器提供定时信号以控制输入开关打开或关闭，并且当输入开关分别断开或闭合时，控制供电开关闭合或断开。 为了在比较频率高的比较器中获得可用于比较器的锁存器，通过在逆变器的电源端子和供电端子之间布置两个另外的电子开关，这两个电子开关由一个定时控制 信号以相对于输入开关闭合的预定延迟而闭合，并在输入开关断开时打开。

公开(公告)号：US5805435A

公开(公告)日：1998-09-08

申请号：US824958

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: H02M3/07 ,  H02M3/18

CPC classification number: H02M3/07

Abstract: A device includes a first line at the supply voltage; a second line at the boost voltage; a booster stage; a supply detecting stage connected to the first line and generating a first level signal when the supply voltage exceeds a first predetermined level; a boost detecting stage connected to the second line and generating a second level signal when the boost voltage exceeds a second predetermined level; a regulating stage enabled by the boost detecting stage; and a pump control stage, which generates a regulating enabling signal for the regulating stage in the absence of the first level signal and in the presence of an enabling signal enabling the boost condition. The regulating stage generates a regulating signal in the presence of the second level signal and the regulating enabling signal, when the boost voltage exceeds a third predetermined level; and the pump control stage generates a pump activating signal for the booster stage in the absence of the first level signal and the regulating signal.

Abstract translation: 设备包括在电源电压下的第一线; 在升压电压下的第二行; 增强阶段; 电源检测级连接到第一线，并且当电源电压超过第一预定电平时产生第一电平信号; 升压检测级，连接到第二线，并且当升压电压超过第二预定电平时产生第二电平信号; 由升压检测级使能的调节级; 以及泵控制级，其在没有第一级信号的情况下产生用于调节级的调节使能信号，并且存在能够进行升压状态的使能信号。 当升压电压超过第三预定电平时，调节级在存在第二电平信号和调节使能信号的情况下产生调节信号; 并且在没有第一电平信号和调节信号的情况下，泵控制级产生用于升压级的泵激活信号。

公开(公告)号：US5805022A

公开(公告)日：1998-09-08

申请号：US713715

申请日：1996-09-13

Applicant: Melchiorre Bruccoleri ,  David Demicheli ,  Marco Demicheli ,  Giuseppe Patti

Inventor： Melchiorre Bruccoleri ,  David Demicheli ,  Marco Demicheli ,  Giuseppe Patti

IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

CPC classification number: H03G3/3026 ,  G11B5/02 ,  H03G1/0088

Abstract: A circuit having a double half-wave rectifier connected to the outputs of a differential amplifier in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier. Two comparators each having an input are connected to an output of the rectifier and a reference input in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs. The circuit also has processing means for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified is not symmetrical.

Abstract translation: 电路具有连接到差分放大器的输出的双半波整流器，以便产生取决于放大器的输出信号的半波幅度的两个量。 每个具有输入的两个比较器连接到整流器的输出和参考输入，以便当相应的半波的幅度大于施加到参考输入的电平时产生相应的输出信号。 电路还具有用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号的处理装置。 当待放大的信号不对称时，可以有利地使用该电路。

公开(公告)号：US5805007A

公开(公告)日：1998-09-08

申请号：US721870

申请日：1996-09-27

Applicant: Gianluca Colli

Inventor： Gianluca Colli

IPC: G06G7/163 ,  G06F7/44 ,  G06G7/16

CPC classification number: G06G7/163

Abstract: A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Abstract translation: 具有四个相乘分支的乘法器，每个分支由缓冲晶体管和由彼此串联布置并连接在两个输出节点和公共节点之间的两个输入晶体管组成。 偏置分支呈现二极管连接的强制晶体管，其栅极端子连接到所有缓冲晶体管的栅极端子，其源极端子连接到公共节点。 强制晶体管迫使输入晶体管在三极管（线性）区域（即，作为压控电阻器）中工作，使得它们导通与各个源极和栅极端子之间的电压降成线性比例的电流，以及通过 输出节点与施加到输入晶体管的控制端的输入电压成比例。 通过将乘法分支交叉耦合到输出节点并减去两个输出电流，获得与两个输入电压的乘积成比例的电流。

公开(公告)号：US5799132A

公开(公告)日：1998-08-25

申请号：US22347

申请日：1993-02-24

Applicant: Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

Inventor： Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

IPC: G05B13/02 ,  G06F9/44 ,  G06G7/12 ,  G06N7/02 ,  G06N7/04 ,  G06G7/00

CPC classification number: G05B13/0275 ,  G06N7/04 ,  Y10S706/90

Abstract: A fuzzy logic electronic controller whereby predetermined membership functions .mu.(x) of logic (X) variables are subjected to so-called inference operations configured essentially as IF-THEN rules with at least one front preposition and at least one rear implication. The controller is of a kind which includes an input or fuzzyfier section having a plurality of inputs for analog or digital signals, a central control unit or fuzzy controller core placed after said input section and being provided with memories, and an output section or defuzzyfier connected to the output of the central unit to convert the results of the inference operations back to analog or digital signals. The controller includes a plurality of fuzzyfiers being disposed in parallel within said input section and each connected to a pair of analog and digital inputs, a plurality of storage modules corresponding in number to said fuzzyfiers and containing data of the front prepositions only of said rules, a fuzzy controller inference unit active in the central control unit to carry out logic operations based on said inference rules of the fuzzy logic by extracting data from said memories through an interfacing circuit, and an additional memory coupled between the fuzzy controller inference unit and the defuzzyfier and adapted to contain data pertaining to the rear (THEN) implications only of said inference rules.

Abstract translation: 一种模糊逻辑电子控制器，其中逻辑（X）变量的预定隶属函数mu（x）经受所谓的推理操作，所述推理操作基本上被配置为具有至少一个前介词和至少一个后置含义的IF-THEN规则。 控制器是一种包括具有用于模拟或数字信号的多个输入的输入或模糊部分，放置在所述输入部分之后并设置有存储器的中央控制单元或模糊控制器核心，以及连接到输出部分或模糊控制器 到中央单元的输出以将推理操作的结果转换回模拟或数字信号。 控制器包括在所述输入部分内并联设置的多个模糊器，每个模糊器连接到一对模拟和数字输入端，多个存储模块数量对应于所述模糊器并且仅包含所述规则的前置介面的数据， 在所述中央控制单元中有效的模糊控制器推理单元，通过接口电路从所述存储器中提取数据，以及耦合在所述模糊控制器推理单元和所述模糊逻辑器之间的附加存储器，基于所述模糊逻辑的所述推理规则执行逻辑运算 并且适于仅包含与所述推理规则有关的后（THEN）影响的数据。

公开(公告)号：US5798959A

公开(公告)日：1998-08-25

申请号：US680393

申请日：1996-07-15

Applicant: Andrea Mario Onetti ,  Sylvia Procurato

Inventor： Andrea Mario Onetti ,  Sylvia Procurato

IPC: H03M1/08 ,  H03G3/00 ,  H03G3/34 ,  H03K17/16 ,  H03K17/693 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/173

CPC classification number: H03K17/16 ,  H03G3/001 ,  H03G3/348 ,  H03H7/25 ,  H03K17/163 ,  H03K19/00361

Abstract: Switching distortion in a digitally controlled attenuator is effectively suppressed and soft-switching in passgate arrays, present at a certain point of a logic signal path, is implemented with a minimum number of additional components. The soft switching in passgate arrays is implemented by driving the control nodes of each passgate by an inverter, at least a current terminal of which is made switchable from the respective supply node to a node onto which an appropriate ramp signal toward the potential of the respective supply potential is produced by a suitable controlled ramp generator. The passgates for switching the current terminals of the inverters are controlled by the logic signal that preexisted the intervening switching on the respective signal line of the passgate, and by its inverse. The preexistent logic value is momentarily stored in a latch that is updated at the end of any new switching process. The switching distortion is suppressed by causing a fast turn-on of the selected switch and a slowed-down turn-off of the deselected switch and by connecting in parallel to the portion of the resistive voltage divider pertaining to the change of output tap a shunt resistance, deselected from the signal path downstream of the selected switch. The deselected switch is driven by a ramp of a preset slope. A circuit sensing the sign of the change of attenuation of the contingent command, configures a pair of switches that deselect the shunt resistance.

Abstract translation: 数字控制的衰减器中的开关失真被有效地抑制，存在于逻辑信号路径的某一点处的通道阵列中的软开关以最小数量的附加组件来实现。 通过门阵列中的软切换通过由逆变器驱动每个通道的控制节点来实现，该逆变器的至少当前端可从相应的电源节点切换到节点，在该节点上施加相应的斜坡信号 供应电位由合适的受控斜坡发生器产生。 用于切换逆变器的电流端子的通孔由预先通过闸门的相应信号线上的插入开关的逻辑信号及其相反来控制。 预先存在的逻辑值被暂时存储在任何新的切换过程结束时被更新的锁存器中。 通过使所选开关的快速接通和取消选择的开关的减速关断并且并联连接到电阻分压器的与输出抽头变化相关的部分分流来分流来抑制开关失真 电阻，从选定开关下游的信号路径中取消选择。 取消选择的开关由预设斜率的斜坡驱动。 感测到偶然命令的衰减变化的符号的电路配置了一对取消选择分流电阻的开关。

公开(公告)号：US5798279A

公开(公告)日：1998-08-25

申请号：US469431

申请日：1995-06-06

Applicant: Giuseppe Crisenza ,  Cesare Clementi

Inventor： Giuseppe Crisenza ,  Cesare Clementi

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L27/115

Abstract: A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

Abstract translation: 一种方法，包括沉积由氧化物层分离的第一和第二多晶硅层的步骤; 选择性地蚀刻第二多晶硅层以形成第一栅极区; 在所述衬底中形成第一衬底区域并相对于所述第一栅极区域侧向地形成; 选择性地蚀刻第一多晶硅层以形成长度大于第一栅极区域的第二栅极区域; 以及在所述衬底中相对于所述第二栅极区域横向地形成并且部分地与所述第一衬底区域重叠的第二衬底区域具有比所述第一衬底区域更高的掺杂水平。

公开(公告)号：US5793675A

公开(公告)日：1998-08-11

申请号：US829935

申请日：1997-04-01

Applicant: Paolo Giuseppe Cappelletti ,  Leonardo Ravazzi

Inventor： Paolo Giuseppe Cappelletti ,  Leonardo Ravazzi

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C29/50004 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

公开(公告)号：US5789288A

公开(公告)日：1998-08-04

申请号：US854584

申请日：1997-05-12

Applicant: Michele Palmieri ,  Paola Galbiati ,  Lodovica Vecchi

Inventor： Michele Palmieri ,  Paola Galbiati ,  Lodovica Vecchi

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8249

CPC classification number: H01L21/266 ,  H01L21/74 ,  H01L21/8249

Abstract: A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it. The process described allows the production of integrated devices with an additional buried layer while utilizing one fewer mask than conventional processes.

Abstract translation: 一种用于通过形成氮化硅层（52）来掺杂P型衬底（50）的方法，通过该层注入N型杂质（图7），形成抗蚀剂掩模（54），其离开至少一个区域 （图8），包含暴露的氮化物层的一部分，首先用不足的能量注入N型杂质，然后以足够的能量穿过氮化物层，使衬底（图9）高 在氧化环境中进行温度处理以在未被氮化物层覆盖的衬底的区域上形成二氧化硅焊盘（55），去除氮化物层并且将P型杂质注入到由衬垫限定的区域中。 然后，该过程继续移除焊盘，并且以常规方式，形成外延层并选择性地掺杂以在其中形成P型和N型区域。 所描述的方法允许使用附加掩埋层的集成器件的生产，同时使用比常规工艺少的掩模。