公开(公告)号：US07536618B2

公开(公告)日：2009-05-19

申请号：US11442515

申请日：2006-05-25

Applicant: Greg Rausch ,  Rob Rabe ,  Jake Klier

Inventor： Greg Rausch ,  Rob Rabe ,  Jake Klier

IPC: G01R31/28

CPC classification number: G01R31/31922 ,  G06F1/08 ,  G11C29/56 ,  G11C29/56012 ,  H03K23/002

Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.

Abstract translation: 信号发生器通过将输入时钟信号通过多个分频器电路产生输出时钟信号，每个分频器电路由触发触发器形成。 通过选择耦合输入时钟信号的触发器来调整输出时钟信号的频率。 重定时器触发器可以耦合在相邻的翻转翻转之间，以重新同步通过触发器耦合的信号。 每个重定时器触发器在其数据输入处从上游触发器的输出接收相应的信号，并且在其时钟输入端接收输入时钟信号。 然后触发器与输入时钟信号同步地将信号施加到下游触发器。 输入信号耦合的最后两个触发器可以预设为各种状态，以将输出时钟信号的相位设置为四相中的一个。

公开(公告)号：US20070300111A1

公开(公告)日：2007-12-27

申请号：US11442515

申请日：2006-05-25

Applicant: Greg Rausch ,  Rob Rabe ,  Jake Klier

Inventor： Greg Rausch ,  Rob Rabe ,  Jake Klier

IPC: G01R31/28

CPC classification number: G01R31/31922 ,  G06F1/08 ,  G11C29/56 ,  G11C29/56012 ,  H03K23/002

Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.

Abstract translation: 信号发生器通过将输入时钟信号通过多个分频器电路产生输出时钟信号，每个分频器电路由触发触发器形成。 通过选择耦合输入时钟信号的触发器来调整输出时钟信号的频率。 重定时器触发器可以耦合在相邻的翻转翻转之间，以重新同步通过触发器耦合的信号。 每个重定时器触发器在其数据输入处从上游触发器的输出接收相应的信号，并且在其时钟输入端接收输入时钟信号。 然后触发器与输入时钟信号同步地将信号施加到下游触发器。 输入信号耦合的最后两个触发器可以预设为各种状态，以将输出时钟信号的相位设置为四相中的一个。

公开(公告)号：US4328509A

公开(公告)日：1982-05-04

申请号：US94119

申请日：1979-11-14

Applicant: Heinz Lehning

Inventor： Heinz Lehning

IPC: H01L21/8224 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H03K19/088 ,  H03K19/091 ,  H03K23/00 ,  H01L29/72

CPC classification number: H03K19/091 ,  H01L29/735 ,  H03K23/002

Abstract: In an n-type base island are provided a p-type emitter stripe and a p-type output collector stripe, with one or more intermediate control collector stripes for switching the current of the output collector. The pattern of control collector stripes can provide AND functions, OR functions or combinations thereof in a single logic element in a single base island. Each output is provided with an npn current reversal transistor in a separate island and if more than one input is to be operated by the output of a logic element, decoupling and fan-out capability are provided by vertical pnp transistors driven by the inverter transistors, which do not require an island completely separate from the inverter transistor, although an isolating barrier stripe can be helpful. A bistable flipflop and a frequency divider cell are shown to illustrate the use of these logic structures. The decoupling referred to can be provided without fan-out amplification by means of diodes.

Abstract translation: 在n型基岛中设置有p型发射极条和p型输出集电极条，具有用于切换输出集电极的电流的一个或多个中间控制集电极条。 控制收集器条纹的图案可以在单个基本岛中的单个逻辑元件中提供AND功能，OR函数或其组合。 每个输出端在单独的岛中设置有npn电流反向晶体管，如果多个输入由逻辑元件的输出端操作，则由反相晶体管驱动的垂直pnp晶体管提供去耦和扇出能力， 其不需要与逆变器晶体管完全分离的岛，尽管隔离屏障条可以是有帮助的。 双稳态触发器和分频器单元被示出来说明这些逻辑结构的使用。 可以通过二极管不提供扇出放大来提供所谓的去耦。

公开(公告)号：US3624838A

公开(公告)日：1971-11-30

申请号：US3624838D

申请日：1966-02-28

Applicant: GEORGE R COGAR

Inventor： COGAR GEORGE R

IPC: G11C11/06 ,  H03K23/00 ,  G11C19/00 ,  H03K21/00

CPC classification number: H03K23/002 ,  G11C11/06007

Abstract: BISTABLE DEVICE IS IN THE SECOND CONDITION BOTH OF THE CONDUCTING ELEMENTS OF THE BIDIRECTIONAL DRIVER ARE TURNED OFF.

THE PRESENT DEVICE IS A STAGE OF A DATA PROCESSING REGISTER WHICH IS CAPABLE OF EITHER INCREMENTING OR DECREMENTING, DEPENDING UPON THE CONDITIONS OF THE PREVIOUS OR SUCCEEDING STAGES. THE PRESENT DEVICE INCORPORATES A BISTABLE DEVICE WHICH PROVIDES TWO IDENTICAL OUTPUT SIGNALS WHEN THE BISTABLE DEVICE IS IN ONE CONDITION AND PROVIDES TWO OTHER KINDS OF OUTPUT SIGNALS EACH OF WHICH IS DIFFERENT FROM THE OTHER AND DIFFERENT FROM THE FIRST MENTIONED OUTPUT SIGNAL WHEN THE BISTABLE DEVICE OPERATES IN THE SECOND CONDITION. THE OUTPUT SIGNALS ARE COUPLED TO A BIDIRECTIONAL CURRENT DRIVER COMPOSED OF TWO CONDUCTING ELEMENTS AND OPERATE ON THAT BIDIRECTIONAL CURRENT DRIVER SUCH THAT WHEN THE BISTABLE DEVICE IS IN THE FIRST CONDITION THE BIDIRECTIONAL CURRENT DRIVER HAS EITHER CONDUCTING ELEMENT AVAILABLE FOR OPERATION WHILE WHEN THE

公开(公告)号：US3617778A

公开(公告)日：1971-11-02

申请号：US3617778D

申请日：1969-06-11

Applicant: FOERDERUNG FORSCHUNG GMBH

Inventor： KOROM ARPAD

IPC: G04G3/02 ,  G04G99/00 ,  G05F3/26 ,  H03K3/281 ,  H03K3/286 ,  H03K3/288 ,  H03K19/088 ,  H03K23/00 ,  H03K23/08

CPC classification number: G04G99/00 ,  G04G3/02 ,  G05F3/265 ,  H03K3/281 ,  H03K3/286 ,  H03K3/288 ,  H03K19/088 ,  H03K23/002

Abstract: Integrated circuit arrangement, wherein the difficulties of building up high ohmic resistors with good properties within integrated circuits have been removed by means of replacing the high ohmic collector resistors and the high ohmic base biasing resistors of conventional integrated circuits by constant current sources in connection with galvanic coupling between transistor stages following one another. The mean collector current and the mean base biasing current of galvanically coupled transistors following one another are delivered by one constant current source. The alternating collector current superposed to this means collector current flows directly and completely into the base-emitter circuit of the galvanic coupled following transistor.

公开(公告)号：US3597627A

公开(公告)日：1971-08-03

申请号：US3597627D

申请日：1970-04-29

Applicant: MARBELITE CO

Inventor： CANE PHILIP

IPC: G08G1/07 ,  H03K23/00 ,  H03K21/00 ,  H03K23/08

CPC classification number: G08G1/07 ,  H03K23/002

Abstract: A three-stage binary counter establishes six different traffic flow conditions without feedback connections by using logical circuitry to maintain two of the traffic conditions for two successive binary counts.

公开(公告)号：US3577085A

公开(公告)日：1971-05-04

申请号：US3577085D

申请日：1969-01-09

Applicant: THEO STUTZ

Inventor： STUTZ THEO

IPC: G06F7/50 ,  G06F7/66 ,  H03K5/26 ,  H03K21/00 ,  H03K21/02 ,  H03K23/00 ,  H03M1/00

CPC classification number: G06F7/50 ,  G06F7/66 ,  G06F2207/4915 ,  H03K5/26 ,  H03K21/00 ,  H03K21/02 ,  H03K23/002 ,  H03M1/00 ,  H03M1/124

Abstract: Two forms of a quinary reduction stage, for reducing the frequency of an input multiphase binary signal by a factor of five are illustrated. One corresponds to the use of a substantially minimum number of elements, while the other corresponds to use of identical binary circuits, all having the same number of inputs. By counting quarter periods of the input signal and half periods of the output signal, a decade reduction stage results. Further, each quinary reduction stage may be connected with a binary reduction stage thus furnishing a decade reduction stage, which may interconnect with other similar ones to constitute a decade forward-reverse counter.

公开(公告)号：US3564385A

公开(公告)日：1971-02-16

申请号：US3564385D

申请日：1969-01-21

Applicant: DANFOSS AS

Inventor： THORSOE FLEMMING

IPC: H02M1/08 ,  H02M7/515 ,  H03K3/29 ,  H03K3/30 ,  H03K3/351 ,  H03K23/00 ,  H02M7/00

CPC classification number: H03K3/29 ,  H02M1/08 ,  H02M7/5152 ,  H03K3/30 ,  H03K3/351 ,  H03K23/002

Abstract: A GENERATOR CONTROLS A THREE PHASE CONVERTER HAVING SIX CONTROLLABLE RECTIFIERS AND A COMMON QUENCHING CONTROLLABLE RECTIFIER. A FREQUENCY EMITTER IS CONTROLLED BY AN INPUT VOLTAGE AND EMITS A CONTROLLED FREQUENCY WHICH IS SIX TIMES THE THREE PHASE FREQUENCY. THE FREQUENCY EMITTER CONTROLS THE COMMON QUENCHING RECTIFIER AND ALSO CONTROLS A THREE STAGE ANNULAR COUNTER. THE THREE OUTPUTS OF THE ANNULAR COUNTER CONTROL THREE BISTABLE MULTIVIBRATOR FREQUENCY DIVIDERS, EACH HAVING TWO OUTPUTS. THE OUTPUT OF EACH FREQUENCY DIVIDER IS CONNECTED TO A GATE CIRCUIT WHICH IN TURN CONTROL ONE OF THE SIX CONTROLLABLE RECTIFIERS. A CORRECTION CIRCUIT INTERCONNECTS THE THREE MULTIVIBRATORS TO INSURE THE PROPER SEQUENCY OF FIRING OF THE SIX CONTROLLABLE RECTIFIERS.

公开(公告)号：US3546697A

公开(公告)日：1970-12-08

申请号：US3546697D

申请日：1968-08-26

Applicant: KING RADIO CORP

Inventor： AKER JOHN L

IPC: G01S13/78 ,  H03H11/12 ,  H03K3/284 ,  H03K23/00 ,  G01S9/14

CPC classification number: H03K23/002 ,  G01S13/787 ,  H03K3/284

公开(公告)号：US3521175A

公开(公告)日：1970-07-21

申请号：US3521175D

申请日：1968-08-26

Applicant: KING RADIO CORP

Inventor： AKER JOHN L

IPC: G01S13/78 ,  H03H11/12 ,  H03K3/284 ,  H03K23/00 ,  H03K5/20

CPC classification number: G01S13/787 ,  H03H11/1213 ,  H03H11/1295 ,  H03K3/284 ,  H03K23/002