公开(公告)号：US07579975B2

公开(公告)日：2009-08-25

申请号：US11954209

申请日：2007-12-11

Applicant: Sandeep Mallya Perdoor ,  Abhaya Kumar ,  Shakti Shankar Rath

Inventor： Sandeep Mallya Perdoor ,  Abhaya Kumar ,  Shakti Shankar Rath

IPC: H03M1/34

CPC classification number: H03M1/0682 ,  H03M1/168 ,  H03M1/361

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract translation: 流水线ADC处理差分信号中的残留块包含多对电容。 在保持工作期间，一对电容器连接到正参考电压，如果输入信号超过相应的阈值电压，另一个电容器连接到负参考电压。 当输入信号不超过相应的阈值电压时，该对的两个电容均连接到正或负参考电压。 结果，可以消除对共模参考电压的需要，并且可以以较小的面积来实现残留块。

公开(公告)号：US20090195424A1

公开(公告)日：2009-08-06

申请号：US12162814

申请日：2007-01-31

Applicant: Geert Van Der Plas ,  Pierluigi Nuzzo ,  Fernando De Bernardinis

Inventor： Geert Van Der Plas ,  Pierluigi Nuzzo ,  Fernando De Bernardinis

IPC: H03M1/12 ,  H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/0607 ,  H03M1/0809 ,  H03M1/361

Abstract: The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.

Abstract translation: 本发明涉及包括至少两个电压比较器装置的模数（A / D）转换器。 每个电压比较器装置被布置成被馈送相同的输入信号并且用于产生自己的内部参考电压。 两个内部参考电压不同。 每个电压比较器被布置用于产生指示所述输入信号的数字近似的位位置的输出信号。

公开(公告)号：US20090146855A1

公开(公告)日：2009-06-11

申请号：US11954209

申请日：2007-12-11

Applicant: Sandeep Mallya Perdoor ,  Abhaya Kumar ,  Shakti Shankar Rath

Inventor： Sandeep Mallya Perdoor ,  Abhaya Kumar ,  Shakti Shankar Rath

IPC: H03M3/00 ,  H03M1/12

CPC classification number: H03M1/0682 ,  H03M1/168 ,  H03M1/361

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract translation: 流水线ADC处理差分信号中的残留块包含多对电容。 在保持工作期间，一对电容器连接到正参考电压，如果输入信号超过相应的阈值电压，另一个电容器连接到负参考电压。 当输入信号不超过相应的阈值电压时，该对的两个电容均连接到正或负参考电压。 结果，可以消除对共模参考电压的需要，并且可以以较小的面积来实现残留块。

公开(公告)号：US07479914B2

公开(公告)日：2009-01-20

申请号：US11853836

申请日：2007-09-12

Applicant: Yasuhide Kuramochi ,  Akira Matsuzawa

Inventor： Yasuhide Kuramochi ,  Akira Matsuzawa

IPC: H03M1/12

CPC classification number: H03M1/0643 ,  A61K38/00 ,  C07K1/22 ,  C07K14/75 ,  H03M1/0658 ,  H03M1/144 ,  H03M1/361 ,  H03M1/46 ,  H03M1/804

Abstract: An A-D converter includes a plurality of comparators, each of which compares an analog input signal to analog threshold values; an upper field determination section which, during an upper determination phase, supplies in parallel to each of the plurality of comparators the plurality of analog threshold values expressing boundaries of ranges corresponding to each data value acquired from the upper field of a number of bits previously designated in the digital output signal, detects whether the analog input signal is associated with one of the ranges based on comparison results by the plurality of comparators, and narrows data values of the upper field to data values corresponding to a range between the largest analog threshold value less than or equal to the analog input signal and the smallest analog threshold value greater than or equal to the analog input signal; and a lower field determination section which, during the lower determination phase, determines values of conversion target bits based on a plurality of comparison results of the plurality of comparators.

Abstract translation: A-D转换器包括多个比较器，每个比较器将模拟输入信号与模拟阈值进行比较; 上场确定部分，在上确定阶段期间并行地向多个比较器中的每一个提供多个模拟阈值，所述多个模拟阈值表示与从先前指定的多个比特数的比特数的上位获取的每个数据值对应的范围的范围 在数字输出信号中，基于多个比较器的比较结果来检测模拟输入信号是否与一个范围相关联，并且将上场的数据值与对应于最大模拟阈值之间的范围的数据值进行窄化 小于或等于模拟输入信号和大于或等于模拟输入信号的最小模拟阈值; 以及下场确定部，其在所述较低确定阶段期间，基于所述多个比较器的多个比较结果来确定转换目标比特的值。

公开(公告)号：US07477177B2

公开(公告)日：2009-01-13

申请号：US11520436

申请日：2006-09-13

Applicant: Yasuhide Kuramochi ,  Akira Matsuzawa

Inventor： Yasuhide Kuramochi ,  Akira Matsuzawa

IPC: H03M1/12

CPC classification number: H03M1/0643 ,  A61K38/00 ,  C07K1/22 ,  C07K14/75 ,  H03M1/0658 ,  H03M1/144 ,  H03M1/361 ,  H03M1/46 ,  H03M1/804

Abstract: An A-D converter that outputs a digital output signal obtained by digitalizing an analog input signal includes a plurality of comparators that each compare the analog input signal and an analog threshold value based on designated digital threshold data, a high-order field determining section that narrows down a data value corresponding to a high-order field of a predetermined bit number in the digital output signal based on a plurality of comparison results obtained by supplying threshold data different from one another to the plurality of comparators, a low-order field computing section that computes a plurality of candidate values for a data value corresponding to a low-order field of a predetermined bit number located at a side lower than the high-order field, and a low-order field determining section that determines a data value corresponding to the low-order field based on the plurality of candidate values.

Abstract translation: 输出通过对模拟输入信号进行数字化而获得的数字输出信号的AD转换器包括多个比较器，每个比较器基于指定的数字阈值数据来比较模拟输入信号和模拟阈值，高阶场确定部分缩小 基于通过向多个比较器提供彼此不同的阈值数据而获得的多个比较结果，对应于数字输出信号中的预定比特数的高阶场的数据值;低阶场计算部分， 计算与位于低于高位场的一侧的预定比特数的低位场对应的数据值的多个候选值，以及低阶场确定部，其确定对应于 基于多个候选值的低阶场。

公开(公告)号：US07466258B1

公开(公告)日：2008-12-16

申请号：US11545228

申请日：2006-10-10

Applicant: Filipp Akopyan ,  Alyssa Apsel ,  Rajit Manohar

Inventor： Filipp Akopyan ,  Alyssa Apsel ,  Rajit Manohar

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03K3/356113 ,  H03K3/3565 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/361

Abstract: A method and apparatus for converting an analog input signal to a digital output signal, provide for simultaneously comparing the input signal to a sequential multiplicity of reference values representing a range of values of the input signal, and asynchronously processing digital results from simultaneous comparison to produce a digital representation of level crossings of the input signal with respect to the multiplicity of reference values.

Abstract translation: 一种用于将模拟输入信号转换为数字输出信号的方法和装置，用于同时将输入信号与表示输入信号的值的范围的连续多个参考值进行比较，并且异步处理来自同步比较的数字结果以产生 相对于多个参考值的输入信号的电平交叉的数字表示。

公开(公告)号：US07446573B1

公开(公告)日：2008-11-04

申请号：US11361643

申请日：2006-02-24

Applicant: Edward E. Miller

Inventor： Edward E. Miller

IPC: G11C7/00

CPC classification number: H03M1/0682 ,  H03M1/361

Abstract: In accordance with an embodiment of the present invention, a comparator system includes a plurality of multiplexers adapted to multiplex a number of differential input signals and a number of differential reference signals. A differencing circuit receives a differential input signal and a differential reference signal from the multiplexers and provides a differential output signal, which is used to provide a differential comparator output signal. A latch may be provided to perform differential-to-single ended conversion on the differential comparator output signal to provide a latch output signal. An output circuit may provide a registered digital output signal based on the latch output signal.

Abstract translation: 根据本发明的实施例，比较器系统包括多个多路复用器，其适用于复用多个差分输入信号和多个差分参考信号。 差分电路从多路复用器接收差分输入信号和差分参考信号，并提供用于提供差分比较器输出信号的差分输出信号。 可以提供锁存器以在差分比较器输出信号上执行差分到单端转换以提供锁存输出信号。 输出电路可以基于锁存输出信号提供注册的数字输出信号。

公开(公告)号：US20080136688A1

公开(公告)日：2008-06-12

申请号：US12019627

申请日：2008-01-24

Applicant: John Philip Tero

Inventor： John Philip Tero

IPC: H03M1/34 ,  H03M7/16

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increase accuracy without significant increasing power consumption and size.

Abstract translation: 通过比较器阵列中的比较器输出的内插，ADC精度增加1位，从而提高精度，而不会显着增加功耗和尺寸。

公开(公告)号：US20080106453A1

公开(公告)日：2008-05-08

申请号：US11889620

申请日：2007-08-15

Applicant: Masao Hotta ,  Tatsuji Matsuura

Inventor： Masao Hotta ,  Tatsuji Matsuura

IPC: H03M1/38

CPC classification number: H03M1/0675 ,  H03M1/144 ,  H03M1/361

Abstract: An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.

Abstract translation: 模拟 - 数字转换器具有数模转换器，第一，第二和第三比较器，以及顺序比较寄存器和控制逻辑电路。 数模转换器产生模拟信号，第一，第二和第三比较器将输入模拟信号与彼此不同的第一，第二和第三模拟信号进行比较。 此外，顺序比较寄存器和控制逻辑电路控制从第一至第三比较器馈送到数模转换器的数字信号，并将数字信号作为数字值输出，该数字值通过使输入的模拟信号经受模拟 数字转换。

公开(公告)号：US07298306B2

公开(公告)日：2007-11-20

申请号：US11388436

申请日：2006-03-24

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: H03M3/00

CPC classification number: H03M1/0673 ,  H03M1/361 ,  H03M3/338 ,  H03M3/424 ,  H03M3/464

Abstract: Quantizers of delta sigma modulators include comparators to quantize a quantizer input signal. Each comparator compares a respective reference signal to the quantizer input signal. A logic processing module determines a quantizer output signal based upon the comparison. During subsequent periods of time, a comparator offset converter alters “reference signal-to-comparator input terminal” associations to reroute respective reference signals from one arrangement of comparator input terminals of at least two (2) of the comparators to a different arrangement of comparator input terminals. The comparator offset converter can randomly alter the reference signal-to-comparator input terminal associations. The comparator offset converter can maintain a 1:1 reference signal-to-comparator input terminal relationship. By maintaining the 1:1 ratio of reference signal-to-comparator input terminal and randomizing the reference signal-to-comparator input terminal associations, the comparator offset converter effectively converts the comparator offset voltage nonlinearities into energies and frequencies that can be constructively processed and improve signal-to-noise ratios.

Abstract translation: ΔΣ调制器的量化器包括量化量化器输入信号的比较器。 每个比较器将相应的参考信号与量化器输入信号进行比较。 逻辑处理模块基于比较来确定量化器输出信号。 在随后的时间段期间，比较器偏移转换器改变“参考信号对比较器输入端子”关联，以将相应参考信号从至少两个比较器的比较器输入端子的一个布置重新路由到比较器的不同布置 输入端子。 比较器偏移转换器可以随机改变参考信号对比较器的输入端子关联。 比较器偏移转换器可以保持1：1参考信号与比较器的输入端子关系。 通过保持参考信号与比较器输入端子的1：1的比例并使参考信号与比较器的输入端子关联随机化，比较器偏置转换器有效地将比较器偏移电压非线性转换成能被建设性地处理的能量和频率， 提高信噪比。