公开(公告)号：US08009769B2

公开(公告)日：2011-08-30

申请号：US11885978

申请日：2006-03-10

申请人： Matthieu Arzel ,  Fabrice Seguin ,  Cyril Lahuec

发明人： Matthieu Arzel ,  Fabrice Seguin ,  Cyril Lahuec

IPC分类号： H04L27/06

CPC分类号： H03M13/2978 ,  H03M13/23 ,  H03M13/27 ,  H03M13/6597

摘要： A method and a device (20) for decoding a frame capable of being split into p sub-frames each consisting of k information symbols, a first n−k redundant symbols and a last n−k redundant symbols. The decoding process uses two individual decoders (21, 23) which concurrently produce extrinsic data (Extr1i, Extr2i) respectively concerning information symbols and interleaved information symbols. The values of the extrinsic data (Extr1i, Extr2i) are refined by cross-feedback of said data to the input of the decoders (21, 23).

摘要翻译： 一种用于对能够被分割成p个子帧的帧进行解码的方法和装置（20），每个子帧由k个信息符号，第一n-k个冗余符号和最后n个k个冗余符号组成。 解码过程使用分别同时产生关于信息符号和交织的信息符号的外在数据（Extr1i，Extr2i）的两个单独的解码器（21,23）。 外部数据（Extr1i，Extr2i）的值通过所述数据的交叉反馈来精确地解码器（21,23）的输入。

公开(公告)号：US20110173507A1

公开(公告)日：2011-07-14

申请号：US12955709

申请日：2010-11-29

申请人： Cheng-Chi Wong ,  Hsi-Chia Chang

发明人： Cheng-Chi Wong ,  Hsi-Chia Chang

IPC分类号： H03M13/27 ,  G06F11/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3972

摘要： An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

摘要翻译： 提供纠错码编码器。 第一编码器对输入信息比特进行编码并产生第一奇偶校验位。 交织器对输入信息比特进行交织并产生置换的信息比特。 第二编码器对置换的信息位进行编码，并产生第二奇偶校验位。 交织器以窗口方式对输入信息比特进行交织，使得输入信息比特在被交织之前被划分为输入信息比特窗口，此后产生具有置换信息比特的置换信息比特窗口。 当输入信息比特窗口根据不同窗口索引特性被分组成组时，每个置换的信息比特窗口的窗口索引具有与其交错的对应的输入信息比特窗口的特征相同的特征。

公开(公告)号：US20110161782A1

公开(公告)日：2011-06-30

申请号：US12650072

申请日：2009-12-30

申请人： Nur Engin

发明人： Nur Engin

IPC分类号： H03M13/05 ,  G06F12/00 ,  G06F11/10

CPC分类号： H03M13/2987 ,  G11C7/1042 ,  G11C8/10 ,  G11C8/12 ,  H03M13/2978 ,  H03M13/6566

摘要： Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.

摘要翻译： 各种实施例涉及turbo解码器中的存储器件以及用于将数据分配到存储器件中的相关方法。 不同的通信标准在采用级联卷积码的块解码时，使用不同大小的数据块。 存储器件有效地使空间最小化，同时通过启用相同大小的多个存储体，能够实现turbo解码器的更高吞吐量。 存储体的数量可能受到存储体中未使用空间的量的​​限制，这可能是IC芯片上的区域的浪费。 使用与数据块的最大值相关联的地址，存储器可以根据最大地址的最高有效位被分割成多个存储器块，并且多个并行SISO解码器与存储器组的数量相匹配。 这可以实现更高的吞吐量，同时最小化IC芯片上的面积。

公开(公告)号：US07715503B2

公开(公告)日：2010-05-11

申请号：US12534604

申请日：2009-08-03

申请人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

发明人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L5/12 ,  H04L23/02

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US20090132893A1

公开(公告)日：2009-05-21

申请号：US12360477

申请日：2009-01-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/45

CPC分类号： H03M13/2978 ,  H03M13/2975 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all block before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed, and when no error is detected, the decoding results are output.

摘要翻译： 在将一帧信息比特分离成多个块的通信系统中的接收装置，对每个块的信息比特进行Turbo编码，并发送结果，并对编码的信息比特进行解码，其中接收装置包括多个解码器，其数量为 小于每帧的块数。 当满足停止解码的条件时，每个解码器对已经由似然度表示的每个块的编码信息比特执行解码处理，执行尚未执行解码的另一个块的编码信息比特的解码处理。 在对每个解码器执行解码次数达到预定的最大重复次数之前，当已经满足所有块的停止解码条件时，所有块的解码结果被串行组合，执行错误检测处理， 并且当没有检测到错误时，输出解码结果。

公开(公告)号：US07499503B2

公开(公告)日：2009-03-03

申请号：US11728519

申请日：2007-03-26

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

IPC分类号： H04L27/36

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US20080222372A1

公开(公告)日：2008-09-11

申请号：US12037573

申请日：2008-02-26

申请人： Udi Shtalrid

发明人： Udi Shtalrid

IPC分类号： G06F12/00

CPC分类号： H03M13/2978 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/653 ,  H03M13/6536 ,  H03M13/6561 ,  H03M13/6566

摘要： A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.

摘要翻译： turbo解码器具有并行的至少两个Bahl，Cocke，Jelinek和Raviv（BCJR）处理器，每个处理器与相应的交织器串行通信。 BCJR处理器和交织器与内部分为非重叠存储器组的存储器模块进行通信。 turbo解码器包括与每个BCJR处理器/交织器的输出通信的各个分类器电路。 分拣机电路从BCJR处理器/交织器接收数据块，并将数据块引导到由交织器分配给数据块的地址指定的存储体。

公开(公告)号：US07180843B2

公开(公告)日：2007-02-20

申请号：US10340752

申请日：2003-01-13

申请人： Satoshi Furuta ,  Katsuhiko Fukuda ,  Akihiro Itakura

发明人： Satoshi Furuta ,  Katsuhiko Fukuda ,  Akihiro Itakura

IPC分类号： G11B5/09 ,  H03M13/03

CPC分类号： H03M13/3905 ,  G11B20/1833 ,  H03M13/2978 ,  H03M13/6561

摘要： An information recording and reproduction apparatus has a turbo decoder that decodes turbo encoded data. The turbo decoder has a number of likelihood ratio calculation units, forward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units, and backward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units. The likelihood ratio calculation units calculate in parallel the likelihood ratio for each of a plurality of data blocks. The forward direction path probability calculation units time-divisionally calculate probabilities of the forward direction paths for the data blocks. The backward direction path probability calculation units time-divisionally calculate probabilities of the backward direction paths for the data blocks.

摘要翻译： 信息记录和再现装置具有解码turbo编码数据的turbo解码器。 涡轮解码器具有多个似然比计算单元，其数目小于似然比计算单元的数量的前向路径概率计算单元，其数量小于该数目的后向路径概率计算单元 的似然比计算单位。 似然比计算单元并行地计算多个数据块中的每一个的似然比。 向前方向路径概率计算单元分时地计算数据块的前向路径的概率。 向后方向路径概率计算单元分时地计算数据块的反向路径的概率。

公开(公告)号：US20060085719A1

公开(公告)日：2006-04-20

申请号：US11248182

申请日：2005-10-13

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/00

CPC分类号： H03M13/2975 ,  H03M13/2978

摘要： A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.

公开(公告)号：US06995693B1

公开(公告)日：2006-02-07

申请号：US10728076

申请日：2003-12-04

申请人： Ray Lynn Cross

发明人： Ray Lynn Cross

IPC分类号： H03M7/34 ,  H03M7/38 ,  H03M13/03

CPC分类号： H03M13/6306 ,  H03M13/2957 ,  H03M13/2978 ,  H04L1/0048 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0631

摘要： Several embodiments of a multiple input diversity decoding apparatus and method are disclosed. In one embodiment, two or more diversity decoders work together to iteratively decode information. Each diversity decoder can include two or more partial decoders. In another embodiment, a plurality of partial decoders work together to iteratively decode information received in a diversity application.

摘要翻译： 公开了多输入分集解码装置和方法的几个实施例。 在一个实施例中，两个或更多个分集解码器一起工作以迭代地解码信息。 每个分集解码器可以包括两个或多个部分解码器。 在另一个实施例中，多个部分解码器一起工作以迭代地解码在分集应用中接收的信息。