公开(公告)号：US11238914B2

公开(公告)日：2022-02-01

申请号：US17107463

申请日：2020-11-30

申请人： Micron Technology, Inc.

发明人： Jason T. Zawodny

IPC分类号： G11C11/40 ,  G11C11/402 ,  G11C11/406 ,  G11C11/403 ,  G11C5/02 ,  G11C7/10 ,  G11C11/407

摘要： The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

公开(公告)号：US11211111B1

公开(公告)日：2021-12-28

申请号：US17038795

申请日：2020-09-30

申请人： Arm Limited

发明人： Rahul Mathur ,  Mudit Bhargava ,  Supreet Jeloka ,  Andy Wangkun Chen

IPC分类号： G11C11/40 ,  G11C11/4076 ,  G11C11/4094 ,  G11C5/02 ,  G11C15/04 ,  G11C11/4097

摘要： A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.

公开(公告)号：US11170838B2

公开(公告)日：2021-11-09

申请号：US16932239

申请日：2020-07-17

申请人： MENTIUM TECHNOLOGIES INC.

发明人： Farnood Merrikh Bayat ,  Jaroslaw Sulima ,  Mirko Prezioso

IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4093 ,  G01R19/00 ,  G01R19/10 ,  G05F1/56 ,  G05F1/575 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/4097 ,  H03K17/22

摘要： A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.

公开(公告)号：US11120866B1

公开(公告)日：2021-09-14

申请号：US17015408

申请日：2020-09-09

申请人： Kioxia Corporation

发明人： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara

IPC分类号： G11C11/40 ,  G11C11/4096 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4074

摘要： According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

公开(公告)号：US11120860B1

公开(公告)日：2021-09-14

申请号：US16987168

申请日：2020-08-06

申请人： Micron Technology, Inc.

发明人： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC分类号： G11C11/40 ,  G11C11/406

摘要： Methods of operating a number of memory devices are disclosed. A method may include adjusting a count of a refresh address counter of at least one memory device of a number of memory devices such that the count of the refresh address counter of the at least one memory device is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. The method may also include receiving, at each of the number of memory devices, a refresh command. Further, the method may include refreshing, at each of the number of memory devices, a row of memory cells indicated by the count of an associated refresh address counter. Related systems and memory modules are also described.

公开(公告)号：US11114152B1

公开(公告)日：2021-09-07

申请号：US17010126

申请日：2020-09-02

申请人： SK hynix Inc.

发明人： Dong Hyuk Kim ,  Sung Lae Oh ,  Yeong Taek Lee ,  Tae Sung Park ,  Soo Nam Jung

IPC分类号： G11C11/40 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4094

摘要： A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

公开(公告)号：US11017840B1

公开(公告)日：2021-05-25

申请号：US16827062

申请日：2020-03-23

申请人： SK hynix Inc.

发明人： Choung Ki Song

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C11/4096

摘要： A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.

公开(公告)号：US10991713B2

公开(公告)日：2021-04-27

申请号：US16298865

申请日：2019-03-11

申请人： TOSHIBA MEMORY CORPORATION

发明人： Satoshi Nagashima ,  Keisuke Nakatsuka ,  Fumitaka Arai ,  Shinya Arai ,  Yasuhiro Uchiyama

IPC分类号： H01L27/11578 ,  G11C11/40 ,  H01L27/1157

摘要： According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US10978120B2

公开(公告)日：2021-04-13

申请号：US16565407

申请日：2019-09-09

申请人： PHISON ELECTRONICS CORP.

发明人： Ming-Chien Huang

IPC分类号： G11C7/22 ,  G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4076

摘要： A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

公开(公告)号：US10957380B2

公开(公告)日：2021-03-23

申请号：US16369034

申请日：2019-03-29

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun-sung Shin ,  Dae-Jeong Kim ,  Ik-Joon Choi

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06 ,  G11C17/18 ,  G11C17/16

摘要： According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.