公开(公告)号：US11600715B2

公开(公告)日：2023-03-07

申请号：US16659124

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Ching Lin ,  Chien-I Kuo ,  Wei Te Chiang ,  Wei Hao Lu ,  Li-Li Su ,  Chii-Horng Li

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L27/088 ,  H01L29/161 ,  H01L21/461 ,  H01L29/08 ,  H01L29/26 ,  H01L29/06

摘要： An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

公开(公告)号：US20230065925A1

公开(公告)日：2023-03-02

申请号：US17867768

申请日：2022-07-19

申请人： Renesas Electronics Corporation.

发明人： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08

摘要： A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n−-type drain region and a gate electrode sandwich the n-type drift region in plan view.

公开(公告)号：US20230065924A1

公开(公告)日：2023-03-02

申请号：US17511613

申请日：2021-10-27

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC分类号： H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

摘要： Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US20230065785A1

公开(公告)日：2023-03-02

申请号：US17555561

申请日：2021-12-20

申请人： GlobalFoundries U.S. Inc.

发明人： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

IPC分类号： H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

摘要： Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

公开(公告)号：US20230058451A1

公开(公告)日：2023-02-23

申请号：US17450842

申请日：2021-10-14

申请人： GlobalFoundries U.S. Inc.

发明人： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC分类号： H01L29/735 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

摘要： Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.

公开(公告)号：US20230054358A1

公开(公告)日：2023-02-23

申请号：US17439054

申请日：2021-06-15

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Gongyi WU ,  Yong LU ,  Xin Xin

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L21/762 ,  H01L23/528 ,  H01L23/532 ,  H01L29/08

摘要： The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

公开(公告)号：US11588052B2

公开(公告)日：2023-02-21

申请号：US16055634

申请日：2018-08-06

申请人： INTEL CORPORATION

发明人： Biswajeet Guha ,  William Hsu ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

摘要： Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g., employing one or more nanowires, nanoribbons, or nanosheets), thereby improving device performance.

公开(公告)号：US11587989B2

公开(公告)日：2023-02-21

申请号：US16929361

申请日：2020-07-15

申请人： Chongqing BOE Display Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xinwei Wu ,  Shicheng Sun ,  Zhen Zhang ,  Wei Zhang ,  Cunzhi Li ,  Jonguk Kwak

IPC分类号： H01L29/08 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

摘要： The present disclosure relates to a display device, a display panel, and a manufacturing method thereof. The display panel includes a substrate, a driving layer, and a display layer. The substrate has an opening area, a transition area surrounding the opening area, and a display area surrounding the transition area. The driving layer is disposed on a side of the substrate and covers at least the transition area and the display area, an area of the driving layer being located in the transition area being provided with a separation groove surrounding the opening area, the separation groove including a first groove body and a second groove body sequentially communicated toward the substrate in a direction perpendicular to the substrate, and a distance between bottom ends of side walls of the first groove body being smaller than a distance between top ends of side walls of the second groove body.

公开(公告)号：US20230050300A1

公开(公告)日：2023-02-16

申请号：US17978576

申请日：2022-11-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417

摘要： Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20230045793A1

公开(公告)日：2023-02-16

申请号：US17797295

申请日：2021-03-03

申请人： ROHM CO., LTD.

发明人： Takeshi ISHIDA

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

摘要： A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n+ type drain contact region and the p type element isolation region.