公开(公告)号：US20240295983A1

公开(公告)日：2024-09-05

申请号：US18646650

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0679

Abstract: A storage product manufactured as a component to be installed in a computing device to provide network storage services. The storage product has a network interface to receive storage access messages from a remote host system, a bus connector connectable via an external computer bus to an external local host system, a local storage device, and a computational storage processor. The storage product is configured to: separate the storage access messages into first messages, second messages, and third messages; provide the first messages to an external local host system to generate fourth messages; and provide the second messages to the computational storage processor to generate fifth messages. To implement network storage services provided via the network interface, the local storage device executes commands in the third messages, the fourth messages from the local host system, and the fifth messages from the computational storage processor.

公开(公告)号：US12081672B2

公开(公告)日：2024-09-03

申请号：US16573855

申请日：2019-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jonathan D. Harms

IPC: H04L9/32 ,  G06Q20/06 ,  G06Q20/38 ,  H04L9/00

CPC classification number: H04L9/3218 ,  G06Q20/0658 ,  G06Q20/389 ,  G06Q2220/10 ,  H04L9/50 ,  H04L2209/56

Abstract: Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US12081113B2

公开(公告)日：2024-09-03

申请号：US17554839

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: H02M1/32 ,  G06F1/30 ,  G11C5/14 ,  H01L23/498 ,  H01L23/50 ,  H02M3/335

CPC classification number: H02M1/32 ,  G06F1/305 ,  G11C5/14 ,  H01L23/49838 ,  H01L23/50 ,  H02M1/322 ,  H02M3/33507

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

公开(公告)号：US12080700B2

公开(公告)日：2024-09-03

申请号：US18147342

申请日：2022-12-28

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US12080373B2

公开(公告)日：2024-09-03

申请号：US17562620

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G11C7/06 ,  G06F21/60 ,  G06F21/78 ,  G11C7/10

CPC classification number: G11C7/065 ,  G06F21/602 ,  G06F21/78 ,  G11C7/1039 ,  G11C7/1063

Abstract: Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command.

公开(公告)号：US12080365B2

公开(公告)日：2024-09-03

申请号：US17048669

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C27/00 ,  G06N3/065 ,  G06N3/08

CPC classification number: G11C27/005 ,  G06N3/065 ,  G06N3/08

Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

公开(公告)号：US12079589B2

公开(公告)日：2024-09-03

申请号：US17859849

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh

IPC: G06F3/06 ,  G06F7/483 ,  G06F7/57 ,  G11C11/409 ,  H03M7/24

CPC classification number: G06F7/483 ,  G06F3/0638 ,  G06F7/57 ,  G11C11/409 ,  H03M7/24 ,  G06F3/0655

Abstract: Systems, apparatuses, and methods related to a memory array data structure for posit operations are described. Universal number (unum) bit strings, such as posit bit string operands and posit bit strings representing results of arithmetic and/or logical operations performed using the posit bit string operands may be stored in a memory array. Circuitry deployed in a memory device may access the memory array to retrieve the unum bit string operands and/or the results of the arithmetic and/or logical operations performed using the unum bit string operands from the memory array. For instance, an arithmetic operation and/or a logical operation may be performed using a first unum bit string stored in the memory array and a second unum bit string stored in the memory array. The result of the arithmetic operation and/or the logical operation may be stored in the memory array and subsequently retrieved.

公开(公告)号：US12079514B2

公开(公告)日：2024-09-03

申请号：US17690691

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Vanaja Urrinkala ,  Sharath Chandra Ambula

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for improved performance in a fragmented memory system are described. The memory system may detect conditions associated with a random access parameter stored at the memory system to assess a level of data fragmentation. The memory system may determine that a random access parameter, such as a data fragmentation parameter, a size of information associated with an access command, a depth of a command queue, a delay duration, or a quantity of commands satisfies a threshold. If one or more of the random access parameters satisfies the threshold, the memory system may transmit a request for the host system to increase an associated clock frequency. The host system may increase the number of commands sent to the memory system in a duration of time. That is, the host system may compensate for a slow-down due to data storage fragmentation by increasing the command processing rate.

公开(公告)号：US12079139B2

公开(公告)日：2024-09-03

申请号：US17984958

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh

IPC: G06F12/10 ,  G06F9/455

CPC classification number: G06F12/10 ,  G06F9/45533 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/1041 ,  G06F2212/657

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. An example method includes receiving a request to store data in a persistent memory device and a non-persistent memory device via an input/output (I/O) device; redirecting the request to store the data to logic circuitry in response to determining that the request corresponds to performance of a hierarchical memory operation; storing in a base address register associated with the logic circuitry, logical address information corresponding to the data responsive to receipt of the redirected request; asserting, by the logic circuitry, an interrupt signal on a hypervisor, the interrupt signal indicative of initiation of an operation to be performed by the hypervisor to control access to the data by the logic circuitry; and writing, based at least in part, on receipt of the redirected request, the data to the persistent memory device and the non-persistent memory device substantially concurrently.

公开(公告)号：US12079134B2

公开(公告)日：2024-09-03

申请号：US18178105

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/08 ,  G06F12/0891

CPC classification number: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.