公开(公告)号：US11923855B2

公开(公告)日：2024-03-05

申请号：US17931864

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar Tiwari ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K3/00 ,  H03K3/037 ,  H03K3/13

CPC classification number: H03K3/0377 ,  H03K3/037 ,  H03K3/13

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

公开(公告)号：US20240071439A1

公开(公告)日：2024-02-29

申请号：US18233522

申请日：2023-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Nitin CHAWLA ,  Promod KUMAR ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/109 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

公开(公告)号：US11909410B2

公开(公告)日：2024-02-20

申请号：US17982242

申请日：2022-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/10

CPC classification number: H03M1/0809 ,  H03M1/0626 ,  H03M1/0648 ,  H03M1/1014

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

公开(公告)号：US11889675B2

公开(公告)日：2024-01-30

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/10 ,  H10B10/00 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

CPC classification number: H10B10/12 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L27/0207

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US11881280B2

公开(公告)日：2024-01-23

申请号：US17534136

申请日：2021-11-23

Applicant: STMicroelectronics International N.V.

Inventor： Shivam Kalla ,  Vikas Rana

IPC: G05F3/02 ,  G05F1/10 ,  G11C5/14 ,  G11C11/56 ,  H02M1/00 ,  H03K5/24 ,  G05F3/26 ,  H02M3/07 ,  G11C16/30

CPC classification number: G11C5/145 ,  G05F3/262 ,  G11C5/147 ,  G11C11/5635 ,  G11C16/30 ,  H02M1/0003 ,  H02M3/07 ,  H03K5/24

Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.

公开(公告)号：US20240012871A1

公开(公告)日：2024-01-11

申请号：US17859769

申请日：2022-07-07

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Antonio DE VITA ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F17/15 ,  G06F7/544

CPC classification number: G06F17/15 ,  G06F7/5443

Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.

公开(公告)号：US20230418559A1

公开(公告)日：2023-12-28

申请号：US17847817

申请日：2022-06-23

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Michele ROSSI ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50

Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

公开(公告)号：US20230386566A1

公开(公告)日：2023-11-30

申请号：US18137191

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386565A1

公开(公告)日：2023-11-30

申请号：US18136507

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/74

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/742

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

公开(公告)号：US11798615B2

公开(公告)日：2023-10-24

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.