公开(公告)号：US5801396A

公开(公告)日：1998-09-01

申请号：US488398

申请日：1995-06-07

Applicant: Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

Inventor： Tsiu Chiu Chan ,  Yu-Pin Han ,  Elmer H. Guritz ,  Richard A. Blanchard

IPC: H01L21/8244 ,  H01L27/06 ,  H01L27/092 ,  H01L27/11 ,  H01L29/04

CPC classification number: H01L27/11 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S438/981

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

公开(公告)号：US20250151395A1

公开(公告)日：2025-05-08

申请号：US18983040

申请日：2024-12-16

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: H10D86/00 ,  H01L21/266 ,  H01L23/528 ,  H10B10/00 ,  H10B20/00 ,  H10D30/01 ,  H10D30/60 ,  H10D30/63 ,  H10D30/69 ,  H10D62/10 ,  H10D62/832 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D86/01

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US12255076B2

公开(公告)日：2025-03-18

申请号：US18435915

申请日：2024-02-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey Arellano ,  Aaron Cadag ,  Ela Mia Cadag

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US12224251B2

公开(公告)日：2025-02-11

申请号：US18531561

申请日：2023-12-06

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey Arellano

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

公开(公告)号：US12223218B2

公开(公告)日：2025-02-11

申请号：US18063028

申请日：2022-12-07

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Benedetto Vigna ,  Mahesh Chowdhary ,  Matteo Dameno

IPC: G06F3/14 ,  G01P1/07 ,  G06F3/12

Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.

公开(公告)号：US12211774B2

公开(公告)日：2025-01-28

申请号：US16848635

申请日：2020-04-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Frederick Ray Gomez ,  Aaron Cadag

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

公开(公告)号：US12211772B2

公开(公告)日：2025-01-28

申请号：US17688013

申请日：2022-03-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Fulvio Vittorio Fontana ,  Davide Maria Benelli ,  Jefferson Sismundo Talledo

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.

公开(公告)号：US12170240B2

公开(公告)日：2024-12-17

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Sismundo Talledo

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US12111158B2

公开(公告)日：2024-10-08

申请号：US18136088

申请日：2023-04-18

Applicant: STMicroelectronics, Inc.

Inventor： Deyou Fang ,  Chao-Ming Tsai ,  Milad Alwardi ,  Yamu Hu ,  David McClure

IPC: G01C19/5726 ,  G01C19/5733 ,  G01C25/00

CPC classification number: G01C19/5726 ,  G01C19/5733 ,  G01C25/005

Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.

公开(公告)号：US12092653B2

公开(公告)日：2024-09-17

申请号：US17472126

申请日：2021-09-10

Applicant: STMicroelectronics, Inc.

Inventor： Davy Choi ,  Yamu Hu ,  Deyou Fang

IPC: G01P21/00 ,  G01P15/125 ,  G01R19/10 ,  G01R31/28

CPC classification number: G01P21/00 ,  G01P15/125 ,  G01R19/10 ,  G01R31/2829

Abstract: In one embodiment, a method for detecting functional state of a microelectromechanical (MEMS) sensor is described. The method includes monitoring an input common-mode feedback (ICMFB) voltage generated by an ICMFB circuit coupled to the MEMS sensor through a plurality of nodes. The method also includes determining, using the monitored ICMFB voltage, whether all of the plurality of nodes of the MEMS sensor are electrically connected to the ICMFB circuit.