公开(公告)号：US5666088A

公开(公告)日：1997-09-09

申请号：US611290

申请日：1996-03-06

Applicant: Luigi Penza

Inventor： Luigi Penza

IPC: H03K3/013 ,  H03K3/03 ,  H03K3/354 ,  H03L7/099 ,  H03B5/04

CPC classification number: H03K3/354 ,  H03K3/013 ,  H03K3/0315

Abstract: Each starved-inverter of a voltage controlled ring oscillator has an output transfer gate associated therewith. The pair of complementary switches composing a transfer gate being controlled in common with the relative current generators of the starved-inverter stage, by a frequency control voltage and by a voltage difference between a supply voltage and the control voltage, respectively. The frequency produced by the oscillator is linearly proportional to the control voltage and inversely proportional to the square root of the supply voltage, for an enhanced noise immunity and improved frequency stability.

Abstract translation: 电压控制环形振荡器的每个饥饿逆变器具有与其相关联的输出传输门。 构成传输门的一对互补开关分别通过频率控制电压和电源电压与控制电压之间的电压差分别与饥饿逆变器级的相对电流发生器共同控制。 由振荡器产生的频率与控制电压成线性比例，并与电源电压的平方根成反比，以增强噪声抗扰度和改善的频率稳定性。

公开(公告)号：US5659501A

公开(公告)日：1997-08-19

申请号：US639931

申请日：1996-04-26

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

Abstract translation: 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5659498A

公开(公告)日：1997-08-19

申请号：US684406

申请日：1996-07-19

Applicant: Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

Inventor： Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C11/00

CPC classification number: G11C7/20 ,  H03K3/356008 ,  H03K3/356104

Abstract: A latch circuit that is intentionally unbalanced, so that a first output reaches ground voltage and a second output reaches a supply voltage. The latch circuit may be used with a fully static low-consumption fuse circuit which reverses the first and second outputs of the latch circuit when the fuse is in an unprogrammed state, but does not change the outputs of the latch circuit in the programmed state. In particular, the latch circuit has a first transistor of a first polarity series connected at a first output node with a second transistor of a second polarity between a supply voltage and a ground voltage. A third transistor of the first polarity is series connected at a second output node with a fourth transistor of the second polarity between the supply voltage and the ground voltage. The gate terminals of the first and second transistors are connected to the second output, while the gate terminals of the third and fourth transistors are connected to the first output. The first and third transistors have thresholds which are mutually different, and the second and fourth transistors have thresholds which are mutually different, so that the first output reaches ground voltage and the second output reaches the supply voltage. This circuit can be combined with a fuse circuit, such as a dual gate transistor.

Abstract translation: 有意不平衡的锁存电路，使得第一输出达到地电压，第二输出达到电源电压。 当熔断器处于未编程状态时，锁存电路可以与完全静态的低功耗熔丝电路一起使用，该电路使锁存电路的第一和第二输出反向，但在编程状态下不改变锁存电路的输出。 特别地，锁存电路具有第一极性串联的第一晶体管，在第一输出节点处连接有电源电压和接地电压之间的第二极性的第二晶体管。 第一极性的第三晶体管在第二输出节点处串联连接在电源电压和接地电压之间的第二极性的第四晶体管。 第一和第二晶体管的栅极端子连接到第二输出端，而第三和第四晶体管的栅极端子连接到第一输出端。 第一和第三晶体管具有相互不同的阈值，并且第二和第四晶体管具有相互不同的阈值，使得第一输出达到接地电压，第二输出达到电源电压。 该电路可以与诸如双栅极晶体管的熔丝电路组合。

公开(公告)号：US5657484A

公开(公告)日：1997-08-12

申请号：US364505

申请日：1994-12-27

Applicant: Flavio Scarra

Inventor： Flavio Scarra

IPC: G06F7/00 ,  G06F9/305 ,  G06F9/312

CPC classification number: G06F9/30029

Abstract: A method for loading the content of any selected cell of a source register to any selected cell of a destination register. The value in the selected source cell is tested for a value of zero. The value of the destination register is then copied into a temporary register. During the copying, the selected destination cell is set to a selected value. The selected destination cell, in the temporary location, is either left unchanged or reset to a complementary value depending on the result of the previous zero test. In either event, the value of the temporary register is then copied to the destination register.

Abstract translation: 一种用于将源寄存器的任何选定单元的内容加载到目的地寄存器的任何选定单元的方法。 测试所选源单元格中的值为零。 然后将目标寄存器的值复制到临时寄存器中。 在复制期间，所选择的目的地单元格被设置为选定的值。 临时位置中所选择的目的地单元格可以保持不变，也可以根据先前零点测试的结果重置为互补值。 在任一情况下，临时寄存器的值将被复制到目标寄存器。

公开(公告)号：US5656969A

公开(公告)日：1997-08-12

申请号：US449855

申请日：1995-05-24

Applicant: Francesco Pulvirenti ,  Gregorio Bontempo ,  Roberto Gariboldi

Inventor： Francesco Pulvirenti ,  Gregorio Bontempo ,  Roberto Gariboldi

IPC: H03K17/567 ,  H03G1/00 ,  H03K17/00 ,  H03K17/042 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03G1/0029 ,  H03G1/0023 ,  H03K17/04206 ,  H03K17/166 ,  H03K2217/0036

Abstract: Power consumption by the driving circuitry of an output stage, employing a slew-rate controlling operational amplifier, is reduced by modulating the level of the current output by the operational amplifier in function of the working conditions of the output stage. Switching delay may also be effectively reduced. An auxiliary current generator forces an additional current through the conducting one of the pair of input transistors of the operational amplifier only during initial and final phases of a transition, essentially when the slew rate control loop ceases to be effective. The boosting of the bias current through the conducting input transistor is determined by the degree of unbalance of the differential input stage of the operational amplifier, without the use of dissipative sensing elements.

Abstract translation: 利用输出级的工作条件，通过调制运算放大器的电流输出电平，降低采用摆率控制运算放大器的输出级的驱动电路的功耗。 切换延迟也可以有效降低。 辅助电流发生器仅在转换的初始和最后阶段迫使额外的电流通过运算放大器的一对输入晶体管中的导通一个电流，基本上当压摆率控制回路不再有效时。 通过导通输入晶体管的偏置电流的升压由运算放大器的差分输入级的不平衡度决定，而不使用耗散感测元件。

公开(公告)号：US5644526A

公开(公告)日：1997-07-01

申请号：US538302

申请日：1995-10-02

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L23/528 ,  H01L27/115 ,  G11C5/02 ,  G11C5/06 ,  G11C11/34 ,  G11C11/50

CPC classification number: H01L27/115 ,  H01L23/528 ,  H01L2924/0002

Abstract: The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors made of a first material with relatively low conductivity and each having a plurality of first electrical connection points arranged along itself and a second corresponding plurality of second conductors made of a second material with relatively high conductivity and each having a plurality of second electrical connection points arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors are interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors.

Abstract translation: 所述集成电路容许大的制造缺陷包括由具有相对低导电性的第一材料制成的第一多个第一导体，并且每个具有沿其自身布置的多个第一电连接点和由第二材料制成的第二对应的多个第二导体 具有相对较高的导电性，并且每个具有沿其自身布置的多个第二电连接点，并且所述多个第一点分别以这样的方式电连接到所述多个第二点，以便降低第一导体的串联电阻，并且第二导体 导体在一些第二连续点之间被中断，以使集成电路的相对较大的区域不被第二导体穿过。

公开(公告)号：US5644267A

公开(公告)日：1997-07-01

申请号：US455850

申请日：1995-05-31

Applicant: Francesco Brianti ,  Roberto Alini ,  Valerio Pisati ,  Paolo Gadducci

Inventor： Francesco Brianti ,  Roberto Alini ,  Valerio Pisati ,  Paolo Gadducci

IPC: H03H11/04 ,  H03F3/68

CPC classification number: H03H11/0433

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract translation: 一种高通滤波器，特别适用于高频应用，并且包括至少一个输入端（IN）和至少一个输出端（OUT）的类型，其间被定义为传递函数（FdT），并被插入一个二次电池 包括一系列跨导级（2,3,4,5）的（18）包括连接在所述二次电池（18）的一对级（2,3）之间的可变电流（iK1，iK2）的发电机电路（29） ）和电压基准（GND）。 所述发生器允许在滤波器（20）的传递函数（FdT）中引入可编程零点。

公开(公告)号：US5638327A

公开(公告)日：1997-06-10

申请号：US412162

申请日：1995-03-28

Applicant: Marco Dallabora ,  Mauro L. Sali ,  Fabio Tassan Caser ,  Corrado Villa

Inventor： Marco Dallabora ,  Mauro L. Sali ,  Fabio Tassan Caser ,  Corrado Villa

IPC: H01L21/8247 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

CPC classification number: G11C16/16 ,  G11C16/0416 ,  H01L27/115 ,  H01L29/7885

Abstract: A flash-EEPROM memory array presenting a NOR architecture wherein the memory cells, organized in rows and columns and having drain regions connected to respective bit lines, source regions connected to a common source line, and control gate regions connected to respective word lines, present an asymmetrical structure wherein one of the source and drain regions presents a highly resistive portion to permit programming and erasing of the cells at different regions. The array includes bias transistors arranged in a row and each connected between a respective bit line and the common source line, for maintaining at the same potential the drain and source regions of the cells connected to the nonaddressed bit lines during programming, and so preventing spurious writing.

Abstract translation: 呈现NOR架构的闪存EEPROM存储器阵列，其中以行和列组织并且具有连接到相应位线的漏极区域，连接到公共源极线路的源极区域和连接到相应字线的控制栅极区域的存储器单元呈现 不对称结构，其中源区和漏区之一呈现高电阻部分，以允许在不同区域对单元进行编程和擦除。 该阵列包括排列成一行并且各自连接在相应的位线和公共源极线之间的偏置晶体管，用于在编程期间将连接到非寻址位线的单元的漏极和源极区域保持在相同的电位，从而防止杂散 写作。

公开(公告)号：US5633834A

公开(公告)日：1997-05-27

申请号：US560324

申请日：1995-11-17

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C11/417 ,  G11C7/22 ,  H04L7/00 ,  G11C8/00

CPC classification number: G11C7/22

Abstract: A device that synchronizes an output stage of an electronic memory by enabling the output stage of the memory device after data has been retrieved from the memory, the memory chip is enabled, and output of the memory data is requested. The device also can enable the output stage of the memory regardless of whether the data has been retrieved from the memory based upon receipt of a forced activation signal, and can enable the output stage of the memory for selected bits.

Abstract translation: 一种通过在从存储器检索到数据之后启用存储器件的输出级来同步电子存储器的输出级的装置，使能存储器芯片，并且请求存储器数据的输出。 无论数据是否已经从接收到强制激活信号而从存储器检索，该设备还可以使能存储器的输出级，并且可以使存储器的输出级能够选择位。

公开(公告)号：US5631588A

公开(公告)日：1997-05-20

申请号：US236227

申请日：1994-04-29

Applicant: Luca Bertolini

Inventor： Luca Bertolini

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/78 ,  H02H9/04 ,  H03K17/00 ,  H03K17/08 ,  H03K17/082 ,  H03K17/615 ,  H03K17/687 ,  H05B41/14

CPC classification number: H02H9/047 ,  H03K17/0822 ,  H03K2217/0036

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract translation: 包括共源FET和共漏极FET在内的准互补对称功率级，在输出的高阻抗条件下电流吸收减小。 上级（公共漏极）晶体管的驱动节点与级的输出节点分离，从而防止在控制节点放电的电流发生器Id在相位期间从连接到输出级的负载吸收电流 的高输出阻抗。 这优选地通过使用其栅极连接到级的输出节点的场效应晶体管来实现，并且被连接以提供从上部公共漏极晶体管的驱动节点的放电发生器提取的电流， 供电节点VDD而不是从电压过驱动节点Vb吸收电源节点。 该替代解决方案避免了高压电源的过度负载，并且在过驱动节点Vb驱动多个输出级时特别有用。