公开(公告)号：US07300745B2

公开(公告)日：2007-11-27

申请号：US10772520

申请日：2004-02-04

Applicant: Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

Inventor： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L27/11539 ,  H01L27/115 ,  H01L27/11526

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract translation: 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。

公开(公告)号：US07294883B2

公开(公告)日：2007-11-13

申请号：US11174084

申请日：2005-06-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Abstract translation: 在非易失性存储单元（110）中，选择栅极晶体管形成为埋入沟道晶体管以增加晶体管电流。

公开(公告)号：US20070249123A1

公开(公告)日：2007-10-25

申请号：US11491137

申请日：2006-07-24

Applicant: Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

Inventor： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

IPC: H01L21/336 ,  H01L21/425 ,  H01L21/3205

CPC classification number: H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78 ,  Y10S438/981

Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

Abstract translation: 提供一种制造凹槽通道晶体管的方法。 首先，在掺杂半导体层和基板上形成硬掩模。 蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。 在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。 进行热氧化处理以形成氧化物层。 氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

公开(公告)号：US20070231998A1

公开(公告)日：2007-10-04

申请号：US11438396

申请日：2006-05-23

Applicant: Yu Chi Chen ,  Neng Yang ,  Hsi Chen

Inventor： Yu Chi Chen ,  Neng Yang ,  Hsi Chen

IPC: H01L21/8242

CPC classification number: H01L28/90 ,  H01L27/10852

Abstract: A method for preparing a capacitor structure comprises forming an opening in a dielectric structure, and forming a cylindrical capacitor including a first conductive layer on the sidewall of the opening, a first dielectric layer on the surface of the first conductive layer, and a second conductive layer on the surface of the first dielectric layer. A top portion of the first conductive layer is selectively removed, and a predetermined portion of the dielectric structure is removed. A second dielectric layer covering the cylindrical capacitor and the dielectric structure is then formed to electrically separate the first conductive layer from the second conductive layer. Subsequently, a portion of the second dielectric layer is removed from the top surface of the second conductive layer, and a third conductive layer is formed on the second dielectric layer and the top surface of the second conductive layer.

Abstract translation: 一种电容器结构的制造方法，其特征在于，在电介质结构体中形成开口，在所述开口侧壁上形成包括第一导电层的圆筒形电容器，在所述第一导电层的表面上形成第一电介质层， 层在第一介电层的表面上。 选择性地去除第一导电层的顶部，并且去除电介质结构的预定部分。 然后形成覆盖圆柱形电容器和电介质结构的第二电介质层，以使第一导电层与第二导电层电分离。 随后，从第二导电层的顶表面去除第二电介质层的一部分，并且在第二电介质层和第二导电层的顶表面上形成第三导电层。

公开(公告)号：US07230295B2

公开(公告)日：2007-06-12

申请号：US11101754

申请日：2005-04-08

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

公开(公告)号：US20070120151A1

公开(公告)日：2007-05-31

申请号：US11668477

申请日：2007-01-30

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract translation: 描述了包括基板，控制栅极层，电荷存储层，隧道层，电荷势垒层，栅极介电层和第一掺杂区域的NVM。 控制栅极层设置在衬底的第一沟槽中; 电荷存储层设置在第一沟槽的侧壁和控制栅极层之间; 隧道层设置在第一沟槽的侧壁和电荷存储层之间; 电荷阻挡层设置在电荷存储层和控制栅极层之间; 栅介电层设置在第一沟槽的底部和控制栅极层之间; 并且第一掺杂区域设置在控制栅极层的一侧的衬底中。

公开(公告)号：US07218564B2

公开(公告)日：2007-05-15

申请号：US10893783

申请日：2004-07-16

Applicant: Jon Allan Faue ,  John D. Heightley

Inventor： Jon Allan Faue ,  John D. Heightley

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: An equalization circuit for a pair of resistive-capacitive data lines includes primary and secondary equalization circuits attached at both ends of the data line pair. A primary equalization circuit at one end of the data line pair receives a primary control signal, and a secondary equalization circuit at the other end of the data line pair receives a secondary control signal, which is different than the primary control signal. The equalization devices in the primary equalization circuit are attached near the read and write amplifiers and operate normally since all the information is available as to whether or not the corresponding data line pair should be equalized. The additional equalization devices in the secondary equalization circuit placed at the other end of the data line pair receive a simpler control signal that lacks the information as to whether or not any particular data line pair is being equalized.

Abstract translation: 用于一对电阻电容数据线的均衡电路包括连接在数据线对的两端的主和次级均衡电路。 数据线对一端的主均衡电路接收主控信号，数据线对另一端的二次均衡电路接收与主控信号不同的二次控制信号。 一次均衡电路中的均衡器件附着在读和写放大器附近并且正常工作，因为所有的信息可用于相应的数据线对是否应该相等。 放置在数据线对的另一端的次级均衡电路中的附加均衡装置接收到更简单的控制信号，其缺少关于任何特定数据线对是否被均衡的信息。

公开(公告)号：US20070090409A1

公开(公告)日：2007-04-26

申请号：US11258119

申请日：2005-10-26

Applicant: Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

Inventor： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L27/105 ,  H01L21/823456 ,  H01L27/1052

Abstract: The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

Abstract translation: 本发明涉及一种半导体器件，其分别包括位于衬底的存储器阵列区域和外围电路区域中的至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度 。 半导体器件还包括位于存储器阵列区域和外围电路区域中的阻挡层，位于外围电路区域中的阻挡层上的未掺杂的氧化物屏障和含硼硅酸盐玻璃，其中 位于存储器阵列区域中的阻挡层上和外围电路区域中未掺杂的氧化物屏障上。

公开(公告)号：US07195964B2

公开(公告)日：2007-03-27

申请号：US11182875

申请日：2005-07-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8238

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11546

Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

Abstract translation: 用于栅极（160）的栅极电介质（150）通过热氧化同时作为另一栅极（140）的表面上的电介质形成。 另一个栅极上的电介质厚度由另一个栅极中的掺杂剂浓度控制。 栅极可以是不同MOS晶体管的栅极，或存储单元的选择栅极和浮置栅极。 还提供其他功能。

公开(公告)号：US07169667B2

公开(公告)日：2007-01-30

申请号：US10631941

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。