公开(公告)号：US20140101380A1

公开(公告)日：2014-04-10

申请号：US13644924

申请日：2012-10-04

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Kjeld Svendsen

IPC: G06F12/00

CPC classification number: G06F13/1626 ,  G06F11/3037 ,  G06F13/1642

Abstract: Systems and methods are provided that facilitate memory storage in a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array writes or retrieves data contained therein based upon the command. The memory controller can monitor multiple banks and manage bank activations. Accordingly, memory access overhead can be reduced and memory devices can be more efficient.

Abstract translation: 提供了便于存储器件中的存储器存储的系统和方法。 该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。 存储器控制器向存储器阵列发送命令，并且存储器阵列基于该命令写入或检索其中包含的数据。 内存控制器可以监控多个银行并管理银行激活。 因此，可以减少存储器访问开销，并且存储器设备可以更有效率。

公开(公告)号：US20140099125A1

公开(公告)日：2014-04-10

申请号：US13645627

申请日：2012-10-05

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Benoit Sevigny

IPC: H04B10/12

CPC classification number: H04B10/2504 ,  G02B13/08 ,  G02B19/0014 ,  G02B19/0085 ,  G02B27/30 ,  H04B10/25

Abstract: An optical system and method disclosed include a first lens component and a second lens component within the receive path or the transmit path. The first lens component includes at least two aspheric surfaces that oppose one another and generate a collimated beam channel. The second lens component generates a converging beam and magnifies the converging beam with a magnification factor that is different from a magnification factor in the other path, either the receive path or the transmit path. The receive path and the transmit path include symmetrical lengths and asymmetrical magnification factors.

Abstract translation: 所公开的光学系统和方法包括在接收路径或发射路径内的第一透镜部件和第二透镜部件。 第一透镜部件包括至少两个彼此相对的非球面，并产生准直的光束通道。 第二透镜部件产生会聚光束，并以不同于另一路径（即接收路径或发送路径）中的放大因子的放大倍率来放大会聚光束。 接收路径和发送路径包括对称长度和不对称放大系数。

公开(公告)号：US20130272447A1

公开(公告)日：2013-10-17

申请号：US13910779

申请日：2013-06-05

Applicant: Applied Micro Circuits Corporation

Inventor： Dariush DABIRI ,  Maged F. BARSOUM

IPC: H03H21/00

CPC classification number: H03H21/0021 ,  H03H21/0012

Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ω1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal φ1 (or its complement). The fundamental-enhanced signal φ1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y-φ1. The fundamental-notched signal y-φ1 is itself enhanced to generate a harmonic-enhanced signal φ2 that is used to notch the fundamental-notched signal y-φ1 again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ω1. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

Abstract translation: 电路和方法在包括未知频率的电磁干扰（EMI）的输入信号y上以频率ω1（也称为“基本”频率）执行自适应频谱增强，以产生基本增强信号phi1（或其补码） 。 此后，在开槽电路（也称为“基本陷波”电路）中使用基本增强信号phi1（或补码）以产生基本缺陷信号y-phi1。 基本缺陷信号y-phi1本身被增强以产生用于在与基本开槽串联连接的一个或多个额外的开槽电路中再次陷波基波切割信号y-phi1的谐波增强信号phi2 电路。 结果（“级联谐波陷波”信号）相对没有EMI噪声（基波和谐波），并被用作自适应电路的误差信号，自适应电路又识别基频ω1。 使用级联谐波陷波信号作为误差信号提高适应性收敛速度。

公开(公告)号：US20030169756A1

公开(公告)日：2003-09-11

申请号：US10092064

申请日：2002-03-05

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Michael D. Scholten

IPC: H04L012/56

CPC classification number: H04L12/4604

Abstract: A system to provide fractional bandwidth data transmission includes a network processor, physical layer device, or link layer device nullnulldata devicenull) and a plurality of link layer devices that are coupled to a plurality of input-output ports. The link layer devices are coupled in a serial daisy chain fashion and pass data via a plurality of data channels. The first linked layer device is coupled to the data device and receives data therefrom and the last linked layer device is coupled to the data device and transmits data thereto forming a ring network that includes all of the link layer devices and the data device. Data received from the data device is contained in data packets that contain a destination identifier and the data. Each link layer device receives input data packets and separates the data packets based on the destination identifier contained therein. Data packets having a destination identifier corresponding to one of the plurality of input-output ports coupled to that particular linked layer device are diverted to the identified input-output port. The remaining data, and any data generated by that link layer device, is provided to the next adjacent down-stream link layer device. Data flow control is provided in an upstream direction from one link layer device to the next adjacent up-stream link layer device as a plurality of status indicators that correspond to the plurality of data channels. Each link layer device is responsive to the plurality of status indicators by not transmitting data on data channels having a corresponding status indicator indicative that no data is to be transmitted.

Abstract translation: 提供分数带宽数据传输的系统包括耦合到多个输入 - 输出端口的网络处理器，物理层设备或链路层设备（“数据设备”）以及多个链路层设备。 链路层设备以串行菊花链方式耦合并且经由多个数据信道传递数据。 第一链接层设备被耦合到数据设备并且从其接收数据，并且最后的链接层设备被耦合到数据设备并且向其发送数据，形成包括所有链路层设备和数据设备的环网。 从数据设备接收的数据包含在包含目的地标识符和数据的数据包中。 每个链路层设备接收输入数据分组，并根据其中包含的目的地标识符分离数据分组。 具有对应于耦合到该特定链接层设备的多个输入 - 输出端口之一的目的地标识符的数据分组被转移到所识别的输入 - 输出端口。 剩下的数据和由该链路层设备产生的任何数据被提供给下一个相邻的下游链路层设备。 在从多个数据通道对应的多个状态指示器的上游方向，将数据流控制从一个链路层设备提供给下一个相邻上行链路层设备。 每个链路层设备通过在具有指示不发送数据的对应状态指示符的数据信道上传送数据来响应于多个状态指示符。

公开(公告)号：US20180184373A1

公开(公告)日：2018-06-28

申请号：US15389165

申请日：2016-12-22

Applicant: Applied Micro Circuits Corporation

Inventor： Francesco CAGGIONI ,  Dimitrios GIANNAKOPOULOS

IPC: H04W52/02 ,  H04W24/02 ,  H04W56/00

CPC classification number: H04W52/0212 ,  H04L1/0053 ,  H04L7/04 ,  H04W24/02 ,  H04W56/001 ,  Y02D70/00

Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.

公开(公告)号：US09948427B2

公开(公告)日：2018-04-17

申请号：US14961228

申请日：2015-12-07

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Bart Zeydel

IPC: H03M13/29 ,  H04L1/00

CPC classification number: H04L1/0054 ,  H03M13/4107 ,  H03M13/6502

Abstract: System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

公开(公告)号：US09880849B2

公开(公告)日：2018-01-30

申请号：US14100228

申请日：2013-12-09

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Richard W. Thaik

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836

Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

公开(公告)号：US20160365970A1

公开(公告)日：2016-12-15

申请号：US15208769

申请日：2016-07-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Moshe Malkin ,  Tarun Gupta

IPC: H04L7/00 ,  H04B1/04 ,  H04L12/26

CPC classification number: H04L7/0087 ,  H04B1/04 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091 ,  H04L43/087

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。

公开(公告)号：US20160335186A1

公开(公告)日：2016-11-17

申请号：US14710837

申请日：2015-05-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Kjeld Svendsen

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/126

Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.

Abstract translation: 各种实施例提供了将数据从主存储器预取到高速缓存的系统，然后将未使用的数据排除到较低级别的高速缓存。 预取系统将预取从主存储器到高速缓存的数据，并且不能立即使用的数据或属于太大以至于不能容纳在高速缓存中的数据集的一部分的数据可被标记为被驱逐到较低级别的高速缓存，其保持 数据可用的时间短于数据必须从主存储器再次加载的时间。 这降低了可用数据预取得太远的成本，并防止高速缓存丢弃。

公开(公告)号：US09397822B1

公开(公告)日：2016-07-19

申请号：US14736754

申请日：2015-06-11

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Moshe Malkin ,  Tarun Gupta

IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26

CPC classification number: H04L7/0087 ,  H04B1/04 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091 ,  H04L43/087

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract translation: 各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。 提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。