公开(公告)号：US20060049620A1

公开(公告)日：2006-03-09

申请号：US11003434

申请日：2004-12-06

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/11 ,  B62D1/19

CPC classification number: B62D1/195

Abstract: A shock absorbing device for steering columns, which has a bracket and a capsule placed around a capsule locking slot of the bracket and fastened along with the bracket to a vehicle body by a locking bolt, is disclosed. The capsule includes an upper plate, a lower plate, and a connector which connects an end of the upper plate to an end of the lower plate. The shock absorbing device further includes a stopper which is provided between the upper plate and the lower plate of the capsule such that the stopper is placed in the capsule locking slot of the bracket. The upper plate of the capsule is bent at an outside edge thereof. The stopper is thinner than the bracket around the capsule locking slot. Furthermore, the upper plate and the lower plate of the capsule are configured such that the upper and lower plates are vertically aligned with each other at outside ends of extensions thereof.

Abstract translation: 公开了一种用于转向柱的减震装置，其具有支架和围绕支架的胶囊锁定槽并且通过锁定螺栓与支架一起固定到车体上的胶囊。 胶囊包括上板，下板和将上板的端部连接到下板的端部的连接器。 该减震装置还包括设置在胶囊的上板和下板之间的止动件，使得止动件被放置在支架的胶囊锁定槽中。 胶囊的上板在其外边缘处弯曲。 塞子比胶囊锁定槽周围的支架更薄。 此外，胶囊的上板和下板被构造成使得上板和下板在其延伸部的外端处彼此垂直对准。

公开(公告)号：US20060005005A1

公开(公告)日：2006-01-05

申请号：US11050477

申请日：2005-02-03

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G06F9/00

CPC classification number: G06F9/4401 ,  G06F8/654 ,  G06F8/66

Abstract: A memory system and corresponding method for executing boot code stored therein are provided, the memory system including a mode decoder, a first memory in signal communication with the mode decoder, a second memory in signal communication with the mode decoder, and a mode generator in signal communication with the mode decoder for generating a signal indicative of selecting one of the first and second memories as the boot memory; and the method for executing boot code including initially booting the system from a first memory, programming a second memory for subsequent booting, programming a mode generator to subsequently boot the system from the second memory, and subsequently booting the system from the second memory.

公开(公告)号：US06975490B2

公开(公告)日：2005-12-13

申请号：US10429829

申请日：2003-05-06

Applicant: Byeong-Hoon Lee ,  Min-Ho So

Inventor： Byeong-Hoon Lee ,  Min-Ho So

IPC: G01R31/02 ,  F24F11/00 ,  F24F11/02 ,  G01R29/18 ,  H02H3/253 ,  H02H7/09 ,  H02H7/00

CPC classification number: H02H3/253 ,  F24F11/30 ,  H02H7/09

Abstract: In an apparatus and a method for detecting a phase state capable of improving reliability of an air conditioner by preventing an abnormal operation of the air conditioner by detecting a phase state (antiphase and open-phase) of three phase AC power supplied to the air conditioner and displaying the detected phase state, the apparatus includes a phase detector for detecting first, second and third phases of a three phase current; an interrupt detector for detecting a falling edge of a pulse signal corresponded to the third phase of the detected first, second and third phases, recognizing an interrupt occurrence by the third phase when the falling edge is detected and generating a counting signal; a counter for counting a pulse signal corresponded to the first and second phases on the basis of the interrupt occurred-third phase according to the counting signal; an antiphase/open-phase detector for detecting a state as a normal connection state, an antiphase state on the basis of a pulse signal corresponded to the first or second phase counted by the counter and detecting an open-phase state on the basis of the interrupt counting times; and a display unit for displaying a message indicating the antiphase state or the open-phase state or the normal connection state on a screen according to a control signal of the antiphase/open-phase detector.

Abstract translation: 在通过检测提供给空调器的三相AC电力的相位状态（反相和开相）来防止空调机的异常运行来检测能够提高空调的可靠性的相位状态的装置和方法中， 并显示所检测的相位状态，所述装置包括用于检测三相电流的第一，第二和第三相位的相位检测器; 用于检测对应于检测到的第一，第二和第三相位的第三相位的脉冲信号的下降沿的中断检测器，当检测到下降沿时识别出第三相位的中断发生并产生计数信号; 根据计数信号，根据中断发生的第三相位计数对应于第一和第二相的脉冲信号的计数器; 用于检测作为正常连接状态的状态的反相/开路相位检测器，基于对应于由计数器计数的第一或第二相位的脉冲信号的反相状态，并基于 中断计数次数; 以及显示单元，用于根据反相/开相检测器的控制信号在屏幕上显示指示反相状态或者开相状态或正常连接状态的信息。

公开(公告)号：US20050007859A1

公开(公告)日：2005-01-13

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。

公开(公告)号：US06831860B2

公开(公告)日：2004-12-14

申请号：US09997080

申请日：2001-11-28

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

IPC: G11C1604

CPC classification number: G11C16/0416 ,  G11C16/08

Abstract: A sector structure of a flash memory device minimizes a layout area in a chip without deteriorating a high-speed operation. The sector structure of the flash memory device includes a plurality of sectors, each sector including memory cell transistors in a cell array block sharing a common bulk region with transistors in a column decoder block.

Abstract translation: 闪存器件的扇区结构使芯片中的布局区域最小化，而不会降低高速操作。 闪存器件的扇区结构包括多个扇区，每个扇区包括与列解码器块中的晶体管共享公共体区的单元阵列块中的存储单元晶体管。

公开(公告)号：US5773852A

公开(公告)日：1998-06-30

申请号：US679564

申请日：1996-07-15

Applicant: Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

Inventor： Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

IPC: H01L29/78 ,  H01L29/72 ,  H01L29/739 ,  H01L29/786 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/7394

Abstract: A shorted anode lateral insulated gate bipolar transistor includes a semiconductor layer of a first conductivity type, a first current electrode, a second current electrode, a first insulation layer, a first gate electrode, a second gate electrode, a first high concentration impurity region of a second conductivity type, a low concentration impurity region of the second conductivity type, a first high concentration impurity region of the first conductivity type, a second high concentration impurity region of the second conductivity type, a third high concentration impurity region of the second conductivity type, and a second high concentration impurity region of the first conductivity type.

Abstract translation: 短路阳极横向绝缘栅双极晶体管包括第一导电类型的半导体层，第一电流电极，第二电流电极，第一绝缘层，第一栅极电极，第二栅极电极，第一高浓度杂质区域 第二导电类型的低浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第二高浓度杂质区，第二导电类型的第二高浓度杂质区， 型和第一导电类型的第二高浓度杂质区。

公开(公告)号：US20170141819A9

公开(公告)日：2017-05-18

申请号：US14803590

申请日：2015-07-20

Applicant: JONG-PIL CHO ,  IL-JONG SONG ,  BYEONG-HOON LEE

Inventor： JONG-PIL CHO ,  IL-JONG SONG ,  BYEONG-HOON LEE

IPC: H04B5/00

CPC classification number: H04B5/0062 ,  H04B5/0031

Abstract: A method of operating a near field communication (NFC) device includes receiving, by the NFC device, a first signal from an NFC reader, transmitting, by the NFC device, a response to the first signal to the NFC reader and changing selectively, by the NFC device, a radio frequency (RF) configuration parameter associated with signal transmission operation during a signal transmission interval, based on determining whether the NFC reader recognizes the response.

公开(公告)号：US08576626B2

公开(公告)日：2013-11-05

申请号：US13570960

申请日：2012-08-09

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪存之一的选择电路。

公开(公告)号：US08046634B2

公开(公告)日：2011-10-25

申请号：US11869990

申请日：2007-10-10

Applicant: Sun-Kwon Kim ,  Byeong-Hoon Lee ,  Ki-Hong Kim

Inventor： Sun-Kwon Kim ,  Byeong-Hoon Lee ,  Ki-Hong Kim

IPC: G06F11/00

CPC classification number: G06F11/00

Abstract: An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal condition detector detects whether at least one operating condition of the integrated circuit card is within one of a suspend region or a reset region. The abnormal condition detector controls an operation of the central processing unit in accordance with the detection.

Abstract translation: 集成电路卡包括中央处理单元，存储器和异常状态检测器。 存储器存储要由中央处理单元处理的数据。 异常状况检测器检测集成电路卡的至少一个工作状态是否在暂停区域或复位区域中的一个内。 异常状态检测器根据检测器控制中央处理单元的操作。

公开(公告)号：US20110225351A1

公开(公告)日：2011-09-15

申请号：US13111489

申请日：2011-05-19

Applicant: Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G06F12/00

CPC classification number: G11C16/20

Abstract: A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.

Abstract translation: 存储卡包括：响应于外部输入的所有命令的第一存储器芯片; 以及响应命令的第二存储器芯片，在外部输入的命令中与数据的读取，编程和擦除操作相关。 存储在第一存储器芯片中的卡识别信息包括对应于第一和第二存储器芯片的尺寸之和的容量信息。 存储卡的多个存储芯片可用于以各种形式设计具有存储容量的存储卡。