公开(公告)号：US20100309038A1

公开(公告)日：2010-12-09

申请号：US12479901

申请日：2009-06-08

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0607 ,  H03M1/167 ,  H03M1/44

Abstract: An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage.

Abstract translation: 提供了模数转换器。 转换器包括第一级，调整单元和数字纠错逻辑。 第一级具有第一感测范围并且接收第一电压以产生第一数字码。 调整单元调整第一级的第一感测范围。 数字纠错逻辑接收和校正第一数字码以产生对应于第一电压的数字码。

公开(公告)号：US20100201553A1

公开(公告)日：2010-08-12

申请号：US12368593

申请日：2009-02-10

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03M1/20

CPC classification number: H03M1/0641 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/207

Abstract: A method for enhancing resolution of digital signals converted from analog signals is provided. The method includes the steps of: converting an analog input signal into N-bit digital outputs, where N is a positive integer; interpolating the N-bit digital outputs to add one or more least significant bit orders for the N-bit digital outputs; generating one or more dither values as least significant bits corresponding to the least significant bit orders; and superimposing the dither values on the interpolation of the N-bit digital outputs. An A/D converter is also disclosed herein.

Abstract translation: 提供了一种用于增强从模拟信号转换的数字信号分辨率的方法。 该方法包括以下步骤：将模拟输入信号转换成N位数字输出，其中N是正整数; 内插N位数字输出，为N位数字输出增加一个或多个最低有效位指令; 产生一个或多个抖动值作为对应于最低有效位顺序的最低有效位; 并将抖动值叠加在N位数字输出的内插上。 本文还公开了A / D转换器。

公开(公告)号：US07733139B2

公开(公告)日：2010-06-08

申请号：US12010554

申请日：2008-01-25

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891

Abstract: A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

Abstract translation: 延迟锁定环电路包括相位频率检测器，采样器，电荷泵，偏置发生器和电压控制元件。 相位 - 频率检测器通过检测输入时钟信号和反馈时钟信号之间的相位差来输出至少一个差分信号。 采样器通过根据输入时钟信号延迟差分信号来输出至少一个采样信号。 电荷泵根据采样信号产生一个控制电压。 偏置发生器根据控制电压产生至少一个偏置电压。 电压控制元件由偏置电压控制，以根据输入时钟信号将反馈时钟信号输出到相位检波器。 还公开了一种在延迟锁定环电路中消除输入时钟信号和输出时钟信号之间的抖动和偏移的方法。

公开(公告)号：US07724063B1

公开(公告)日：2010-05-25

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US20090284314A1

公开(公告)日：2009-11-19

申请号：US12123335

申请日：2008-05-19

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03F3/38

CPC classification number: H03F1/0261 ,  H03F1/305 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45138 ,  H03F2203/45528

Abstract: An audio amplifier includes a timing control circuit, an amplifying circuit, and a bias control circuit. The timing control circuit generates a first power down signal and a second power down signal, in which the first power down signal is asserted before the second power down signal is asserted. The amplifying circuit receives a bias voltage to amplify an audio signal and is deactivated when the first power down signal is asserted. The bias control circuit provides the bias voltage for the amplifying circuit and is deactivated when the second power down signal is asserted.

Abstract translation: 音频放大器包括定时控制电路，放大电路和偏置控制电路。 定时控制电路产生第一掉电信号和第二掉电信号，其中在断言第二掉电信号之前断言第一掉电信号。 放大电路接收偏置电压以放大音频信号，并且当第一掉电信号被断言时，放大电路被去激活。 偏置控制电路为放大电路提供偏置电压，并且在断言第二次掉电信号时被去激活。

公开(公告)号：US20090212864A1

公开(公告)日：2009-08-27

申请号：US12071485

申请日：2008-02-21

Applicant: Chih-Haur Huang ,  Chung-Ming Huang

Inventor： Chih-Haur Huang ,  Chung-Ming Huang

IPC: H03F3/45

CPC classification number: H03F3/4521 ,  H03F3/3022 ,  H03F3/45704 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45078 ,  H03F2203/45586 ,  H03F2203/45616

Abstract: A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly.

Abstract translation: 提供了在接收机中使用的前置放大器。 前置放大器包括输入电路和输出电路。 输入电路接收输入差分电压对，当输入差分电压对的公共电压高于参考电压时将其拉下。 输出电路接收从输入电路输出的输入差分电压对，以相应地拉高或低电平。

公开(公告)号：US07576609B1

公开(公告)日：2009-08-18

申请号：US12071485

申请日：2008-02-21

Applicant: Chih-Haur Huang ,  Chung-Ming Huang

Inventor： Chih-Haur Huang ,  Chung-Ming Huang

IPC: H03F3/45

CPC classification number: H03F3/4521 ,  H03F3/3022 ,  H03F3/45704 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45078 ,  H03F2203/45586 ,  H03F2203/45616

Abstract: A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly.

Abstract translation: 提供了在接收机中使用的前置放大器。 前置放大器包括输入电路和输出电路。 输入电路接收输入差分电压对，当输入差分电压对的公共电压高于参考电压时将其拉下。 输出电路接收从输入电路输出的输入差分电压对，以相应地拉高或低电平。

公开(公告)号：US07570093B1

公开(公告)日：2009-08-04

申请号：US12076319

申请日：2008-03-17

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/089 ,  H03L7/10

Abstract: A delay-locked loop detector detects a control voltage of a delay-locked loop, in which the delay-locked loop generates an output clock signal according to a delay time that is controlled by the control voltage. The delay-locked loop detector includes a voltage detector, a switch, and a counter. The voltage detector detects the control voltage. The switch passes the control voltage to the voltage detector. The counter counts a constant period of time, in which the counter enables the switch to pass the control voltage to the voltage detector after the constant period of time.

Abstract translation: 延迟锁定环路检测器检测延迟锁定环路的控制电压，其中延迟锁定环路根据由控制电压控制的延迟时间产生输出时钟信号。 延迟锁定环路检测器包括电压检测器，开关和计数器。 电压检测器检测控制电压。 开关将控制电压传递到电压检测器。 计数器计数恒定的时间段，其中计数器使得开关在恒定时间段之后将控制电压传递到电压检测器。

公开(公告)号：US20090189657A1

公开(公告)日：2009-07-30

申请号：US12010554

申请日：2008-01-25

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891

Abstract: A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

Abstract translation: 延迟锁定环电路包括相位频率检测器，采样器，电荷泵，偏置发生器和电压控制元件。 相位 - 频率检测器通过检测输入时钟信号和反馈时钟信号之间的相位差来输出至少一个差分信号。 采样器通过根据输入时钟信号延迟差分信号来输出至少一个采样信号。 电荷泵根据采样信号产生一个控制电压。 偏置发生器根据控制电压产生至少一个偏置电压。 电压控制元件由偏置电压控制，以根据输入时钟信号将反馈时钟信号输出到相位检波器。 还公开了一种在延迟锁定环电路中消除输入时钟信号和输出时钟信号之间的抖动和偏移的方法。

公开(公告)号：US20090146705A1

公开(公告)日：2009-06-11

申请号：US11951225

申请日：2007-12-05

Applicant: Chih-Haur Huang

Inventor： Chih-Haur Huang

IPC: H03L7/06

CPC classification number: H03L7/093 ,  H03L7/0812

Abstract: A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register outputs a digital signal in accordance with a phase difference between an input signal and a feedback signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input signal and an output signal in a delay locked loop circuit is also disclosed.

Abstract translation: 提供了延迟锁定环电路（DLL）。 延迟锁定环路包括移位寄存器，数模转换器和压控延时线。 移位寄存器根据输入信号和反馈信号之间的相位差输出数字信号。 数模转换器将从移位寄存器输出的数字信号转换为控制电压。 电压控制延迟线根据数模转换器传输的控制电压输出反馈信号。 还公开了一种在延迟锁定环电路中消除输入信号和输出信号之间的抖动和偏移的方法。