公开(公告)号：US06833578B1

公开(公告)日：2004-12-21

申请号：US10733216

申请日：2003-12-11

Applicant: Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu ,  Chung-Wei Chang ,  Tien-Lu Lin ,  Kuo-Ching Huang ,  Wen-Cheng Chen ,  Tsung-Hsun Huang ,  Hsiao-Hui Tseng

Inventor： Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu ,  Chung-Wei Chang ,  Tien-Lu Lin ,  Kuo-Ching Huang ,  Wen-Cheng Chen ,  Tsung-Hsun Huang ,  Hsiao-Hui Tseng

IPC: H01L27108

CPC classification number: H01L28/57 ,  H01L27/11 ,  H01L28/90

Abstract: A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.

Abstract translation: 一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。 间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。 在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

公开(公告)号：US06638813B1

公开(公告)日：2003-10-28

申请号：US10059825

申请日：2002-01-29

Applicant: Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

Inventor： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

Abstract: A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

Abstract translation: 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

公开(公告)号：US06433665B1

公开(公告)日：2002-08-13

申请号：US09839702

申请日：2001-04-23

Applicant: Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

Inventor： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

IPC: H01F500

Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

公开(公告)号：US06420226B1

公开(公告)日：2002-07-16

申请号：US10020753

申请日：2001-12-12

Applicant: Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

Inventor： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

IPC: H01L218244

CPC classification number: H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

Abstract: A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

Abstract translation: 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

公开(公告)号：US06403416B1

公开(公告)日：2002-06-11

申请号：US09226279

申请日：1999-01-07

Applicant: Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

Inventor： Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

IPC: H01L218242

CPC classification number: H01L28/91

Abstract: A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC: H01L2976

CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

Abstract: A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US06278352B1

公开(公告)日：2001-08-21

申请号：US09359892

申请日：1999-07-26

Applicant: Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

Inventor： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC: H01F500

CPC classification number: H01F5/003

Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

Abstract translation: 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US06248673B1

公开(公告)日：2001-06-19

申请号：US09511334

申请日：2000-02-23

Applicant: Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

Inventor： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

IPC: H01L21469

CPC classification number: H01L29/518 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31629 ,  H01L21/324 ,  Y10S438/958

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device. The method is a “pure H2 (100%)” alloy recipe to use after contact opening or metal-1 formation.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成微电子器件。 然后在微电子器件上形成由钝化介电材料形成的钝化介电层，该钝化介电材料选自氟硅酸盐玻璃（FSG）钝化介电材料，大气压化学气相沉积（APCVD）钝化介电材料，低于大气压的化学气相沉积 （SACVD）钝化介电材料和旋涂玻璃（SOG）钝化介电材料以从微电子器件形成钝化的微电子器件。 最后，在使用采用包含氢的气氛的热退火方法的同时进行退火，该钝化微电子器件形成稳定的钝化微电子器件。 该方法是在接触开口或金属-1形成之后使用的“纯H 2（100％）”合金配方。

公开(公告)号：US6080647A

公开(公告)日：2000-06-27

申请号：US34927

申请日：1998-03-05

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6046062A

公开(公告)日：2000-04-04

申请号：US373246

申请日：1999-08-12

Applicant: Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

Inventor： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/14

Abstract: This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

Abstract translation: 本发明涉及集成电路器件的特性，更具体地说，涉及一种用于在FET器件的阈值电压特性中监测不可接受的扭结行为的改进方法，这可能是由于栅极氧化物厚度减小和衬底掺杂浓度降低引起的 沿着由STI界定的频道区域的长度。 这是通过将一对漏极电流与栅极电压特性作为衬底电压的两个值的函数来实现的。 在两个曲线之间的相对电压偏移在远低于扭结的漏极电流的值处以及远远高于扭结的漏极电流的值进行比较。 扭结行为的定量程度由对应于远低于扭结的漏极电流值的电压偏移量超过相应于低于扭结线圈的漏极电流的值的电压偏移量来确定多大。