公开(公告)号：US20110030064A1

公开(公告)日：2011-02-03

申请号：US12780986

申请日：2010-05-17

申请人： Sang-hyup KWAK ,  Kwang-il PARK ,  Seung-jun BAE

发明人： Sang-hyup KWAK ,  Kwang-il PARK ,  Seung-jun BAE

IPC分类号： G06F12/14 ,  G11C7/00 ,  G06F12/00

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C11/4096

摘要： A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.

摘要翻译： 数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据 来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集 掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。 数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

公开(公告)号：US20110001562A1

公开(公告)日：2011-01-06

申请号：US12817760

申请日：2010-06-17

申请人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

发明人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/45179 ,  H03F3/45654 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45382 ,  H03F2203/45384 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45702

摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.

摘要翻译： 具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。 比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。 复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。 参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。 控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

公开(公告)号：US20100329049A1

公开(公告)日：2010-12-30

申请号：US12820364

申请日：2010-06-22

申请人： YOUNG-SOO SOHN ,  Jeong-Don Lim ,  Kwang-Il Park

发明人： YOUNG-SOO SOHN ,  Jeong-Don Lim ,  Kwang-Il Park

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/109 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

摘要翻译： 半导体存储器件包括提供省电效果的等待时间控制器。 等待时间控制器包括先进先出（FIFO）寄存器。 在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

公开(公告)号：US20100237902A1

公开(公告)日：2010-09-23

申请号：US12719953

申请日：2010-03-09

申请人： Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

发明人： Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

IPC分类号： H03K19/003 ,  G01R35/00

CPC分类号： H04L25/0278

摘要： A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

摘要翻译： 半导体器件包括多个焊盘，其中外部参考电阻器连接到焊盘的第一焊盘，阻抗校准单元被配置为产生对应于参考电阻器的阻抗的阻抗校准代码，并将阻抗校准代码输出到 在正常操作模式期间的代码传输线，以及阻抗匹配单元，被配置为在正常操作模式期间响应于阻抗校准码执行阻抗匹配操作。 阻抗校准单元被配置为在测试操作模式期间响应于测试信号将测试代码输出到代码传输线。 阻抗匹配单元被配置为串行化测试代码，以在测试操作模式期间响应于测试信号将串行测试代码输出到每个其它焊盘。

公开(公告)号：US20100220485A1

公开(公告)日：2010-09-02

申请号：US12730856

申请日：2010-03-24

申请人： Do-Hyung Kim ,  Chung-Hooon Lee ,  Keon-Young Lee ,  Kwang-Il Park

发明人： Do-Hyung Kim ,  Chung-Hooon Lee ,  Keon-Young Lee ,  Kwang-Il Park

IPC分类号： F21V13/04

CPC分类号： G02B19/0071 ,  G02B19/0028 ,  G02B19/0061 ,  H01L33/54 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/19107 ,  H01L2924/00014

摘要： The present invention relates to a side illumination lens and a luminescent device using the same, and provides a body, a total reflection surface with a total reflection slope with respect to a central axis of the body, and a linear and/or curved refractive surface(s) formed to extend from a periphery of the total reflection surface; and a luminescent device including the lens. According to the present invention, a lens with total internal reflection surfaces with different slopes, and a linear and/or curved refractive surface(s) allows light emitted forward from a luminescent chip to be guided to a side of the lens. Further, a linear surface(s) formed in a direction perpendicular or parallel to a central axis of a lens and a curved surface are formed on an edge of the lens so that a process of fabricating the lens is facilitated, thereby reducing a defective rate and fabrication costs of the lens.

摘要翻译： 本发明涉及一种侧面照明透镜及其使用该发光装置的发光装置，其特征在于，具有相对于所述主体的中心轴线具有全反射斜率的全身反射面以及直线和/或弯曲的折射面 形成为从全反射表面的周边延伸; 以及包括该透镜的发光装置。 根据本发明，具有具有不同斜率的全内反射表面以及线性和/或弯曲折射表面的透镜允许从发光芯片向前发射的光被引导到透镜的一侧。 此外，在透镜的边缘上形成在垂直于或平行于透镜的中心轴线的方向上形成的线性表面，从而便于制造透镜的工艺，从而降低了缺陷率 和镜头的制造成本。

公开(公告)号：US07656742B2

公开(公告)日：2010-02-02

申请号：US12128464

申请日：2008-05-28

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC分类号： G11C8/00

CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US07619456B2

公开(公告)日：2009-11-17

申请号：US11826511

申请日：2007-07-16

申请人： Byung-Guk Kim ,  Lee-Sup Kim ,  Kwang-Il Park

发明人： Byung-Guk Kim ,  Lee-Sup Kim ,  Kwang-Il Park

IPC分类号： H03H11/16 ,  H03K5/13 ,  H03K3/00

CPC分类号： H03K5/15013

摘要： A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.

摘要翻译： 多相信号发生器可以包括配置成接收第一差分输入信号和第二差分输入信号的占空比控制缓冲器，并且基于控制电压产生具有可变占空比的第一差分输出信号和第二差分输出信号， 第一边缘组合器，被配置为基于相应的第一和第二差分输出信号的第一边缘产生第一脉冲信号;第二边缘组合器，被配置为基于相应的第一和第二差分输出信号的第二边缘产生第二脉冲信号， 以及控制电压发生器，被配置为响应于通过对所述第一和第二脉冲信号执行逻辑运算而获得的逻辑信号来产生所述控制电压。

公开(公告)号：US20090271652A1

公开(公告)日：2009-10-29

申请号：US12482265

申请日：2009-06-10

申请人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

发明人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

IPC分类号： G06F1/04 ,  G06F1/08

CPC分类号： G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

摘要翻译： 确定存储器件的数据输出之间的定时偏移的方法可以包括以小于用于将非预定数据写入存储器件的正常工作频率的第一工作频率将预定数据模式写入存储器件。 读取存储器件，以大于第一工作频率的第二工作频率输出预定数据模式，并且大约等于用于从存储器件读取非预定数据的正常工作频率。 基于从存储器件提供预定数据的实际时间，在存储器件的输出之间确定定时偏移。

公开(公告)号：US20090267813A1

公开(公告)日：2009-10-29

申请号：US12453109

申请日：2009-04-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M7/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US07463072B2

公开(公告)日：2008-12-09

申请号：US11566651

申请日：2006-12-04

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03B1/00

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

摘要翻译： 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。