公开(公告)号：US20150363517A1

公开(公告)日：2015-12-17

申请号：US14739347

申请日：2015-06-15

申请人： Lawrence T. Clark ,  Dan Wheeler Patterson ,  Chandarasekaran Ramamurthy ,  Srivatsan Chellappa

发明人： Lawrence T. Clark ,  Dan Wheeler Patterson ,  Chandarasekaran Ramamurthy ,  Srivatsan Chellappa

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.

摘要翻译： 本公开一般涉及具有计算机多模冗余（MMR）流水线电路的计算机集成电路（IC）的物理表示的计算机化系统和方法。 电子计算机IC的IC布局最初是通过电子设计自动化（EDA）程序生成的。 然后，在MMRSCSSE布局变得不稳定之后，多模式冗余自校正顺序状态元素（MMRSCSSE）布局变得不可移动，而从IC布局中删除初始冗余组合逻辑电路（CLC）布局。 首先放置MMRSCSSE布局，然后使它们变得不漂亮，剩下的逻辑可以重新放置并优化，而不会影响关键的节点间距。 因此，所描述的方法提供了一种更有效的方法来创建计算机IC的IC布局，同时保持关键的节点间隔。

公开(公告)号：US08860575B2

公开(公告)日：2014-10-14

申请号：US13306750

申请日：2011-11-29

申请人： David R. Allee ,  Lawrence T. Clark ,  Terry L. Alford ,  Constantine A. Balanis ,  James T. Aberle ,  Kevin Baugh

发明人： David R. Allee ,  Lawrence T. Clark ,  Terry L. Alford ,  Constantine A. Balanis ,  James T. Aberle ,  Kevin Baugh

IPC分类号： G08B13/14 ,  G06K19/077 ,  G06K19/02 ,  H04W52/02

CPC分类号： G06K19/07766 ,  G06K19/025 ,  G06K19/027 ,  H04W52/0235

摘要： Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein.

摘要翻译： 本文描述了灵活识别系统的实施例。 本文还公开了其它实施例和相关方法。

公开(公告)号：US08791718B2

公开(公告)日：2014-07-29

申请号：US13487859

申请日：2012-06-04

申请人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

发明人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

IPC分类号： H03K19/003

CPC分类号： G06F17/5072 ,  G06F17/505 ,  H03K19/00315

摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states.The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs有一个自我纠正机制来防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

公开(公告)号：US08645878B1

公开(公告)日：2014-02-04

申请号：US13592122

申请日：2012-08-22

申请人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

发明人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

IPC分类号： G06F17/50

CPC分类号： H01L21/22 ,  G06F17/505 ,  H01L21/266 ,  H01L29/7816

摘要： Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

公开(公告)号：US20130154739A1

公开(公告)日：2013-06-20

申请号：US13770482

申请日：2013-02-19

申请人： Lawrence T. Clark ,  Scott E. Thompson

发明人： Lawrence T. Clark ,  Scott E. Thompson

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45183 ,  H03F3/45273 ,  H03F2200/375 ,  H03F2203/45344 ,  H03F2203/45454 ,  H03F2203/45506 ,  H03F2203/45674 ,  H03F2203/45676

摘要： Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

公开(公告)号：US08462565B2

公开(公告)日：2013-06-11

申请号：US13083427

申请日：2011-04-08

申请人： Sameer M. Venugopal ,  David R. Allee ,  Lawrence T. Clark

发明人： Sameer M. Venugopal ,  David R. Allee ,  Lawrence T. Clark

IPC分类号： G11C7/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  Y10T29/49117

摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. In one example, a method for providing an integrated circuit can comprise providing a memory cell coupled to a first bitline and to a second bitline, and at least one of (a) providing a read assist mechanism configured to couple to the memory cell via the first and second bitlines, or (b) providing a memory reset mechanism configured to couple to the memory cell via the first and second bitlines. Providing the memory cell can comprise providing a first transistor comprising a first threshold voltage, providing a second transistor comprising a second threshold voltage, and cross-coupling the first and second transistors of the memory cell together. A difference between the first and second threshold voltages can correspond to a logic state of the memory cell. Other embodiments, examples, and related methods are also disclosed herein.

摘要翻译： 本文描述了差分阈值电压非易失性存储器及相关方法的实施例和示例。 在一个示例中，用于提供集成电路的方法可以包括提供耦合到第一位线和第二位线的存储器单元，以及（a）提供读取辅助机构中的至少一个，所述读取辅助机构被配置为经由所述第一位线耦合到所述存储器单元 第一和第二位线，或（b）提供被配置为经由第一和第二位线耦合到存储器单元的存储器复位机构。 提供存储器单元可以包括提供包括第一阈值电压的第一晶体管，提供包括第二阈值电压的第二晶体管，以及将存储器单元的第一和第二晶体管交叉耦合在一起。 第一和第二阈值电压之间的差异可以对应于存储器单元的逻辑状态。 本文还公开了其它实施例，示例和相关方法。

公开(公告)号：US20130111282A1

公开(公告)日：2013-05-02

申请号：US13808438

申请日：2011-07-19

申请人： Lawrence T. Clark ,  Yu Cao

发明人： Lawrence T. Clark ,  Yu Cao

IPC分类号： G11C29/08

CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/28 ,  G11C29/40 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/2602

摘要： Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.

摘要翻译： 公开了用于在静态随机存取存储器（SRAM）单元上执行并行测试操作的系统和方法。 通常，每个并行测试操作是对SRAM单元的块并行或同时执行的测试操作。 在一个实施例中，SRAM单元被布置成多行和多列，其中列进一步布置成一个或多个列组。 用于每个并行测试操作的SRAM单元的块包括两行或多行中的SRAM单元，同一列组中的两列或更多列中的SRAM单元，或两行或多行中的两个SRAM单元或两个或更多行中的SRAM单元 更多列在同一列组中。

公开(公告)号：US08112643B2

公开(公告)日：2012-02-07

申请号：US12232646

申请日：2008-09-22

申请人： Dennis M. O'Connor ,  Michael W. Morrow ,  Lawrence T. Clark

发明人： Dennis M. O'Connor ,  Michael W. Morrow ,  Lawrence T. Clark

IPC分类号： G06F1/26

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/171

摘要： A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.

摘要翻译： 处理引擎将一行或多行软件指令读取到指令高速缓存中。 基于高速缓存的内容，可能需要的功能单元被识别为可操作以执行存储在指令高速缓存内的至少一个软件指令的功能单元。 不需要的功能单元被识别为不能用于执行存储在指令高速缓存内的软件指令的功能单元。 对被确定为处于低功率状态的潜在需要的功能单元中的所选择的功能单元启动功率增加。 对被确定为处于可操作功率状态的不需要的功能单元中的所选功能单元启动功率减小。

公开(公告)号：US20110261635A1

公开(公告)日：2011-10-27

申请号：US13083427

申请日：2011-04-08

申请人： Sameer M. Venugopal ,  David R. Allee ,  Lawrence T. Clark

发明人： Sameer M. Venugopal ,  David R. Allee ,  Lawrence T. Clark

IPC分类号： G11C7/00 ,  H01R43/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  Y10T29/49117

摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.

公开(公告)号：US07738020B1

公开(公告)日：2010-06-15

申请号：US12563337

申请日：2009-09-21

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： H04N3/14 ,  H04N5/238

CPC分类号： H04N5/3535 ,  H01L27/14609 ,  H04N5/2353

摘要： An imaging system includes a photocell circuit. The photocell circuit includes a photodetector circuit. The photodetector circuit includes an input configured to receive incident light. A first terminal communicates with a sample node. A second terminal communicates with a monitor node. A sampling circuit is configured to drive the sample node to a first reset value at a first time in response to a first reset signal. The sampling circuit allows the first reset value to decay at a second time subsequent to the first time. A monitor circuit is configured to drive the monitor node to a second reset value at the first time in response to a second reset signal. The monitor circuit allows the second reset value to decay at the second time. The monitor circuit detects a third time when the monitor node decays to a predetermined stop value subsequent to the second time.

摘要翻译： 成像系统包括光电池电路。 光电管电路包括光电检测器电路。 光电检测器电路包括被配置为接收入射光的输入。 第一终端与样本节点进行通信。 第二终端与监视器节点进行通信。 采样电路被配置为响应于第一复位信号在第一时间将采样节点驱动到第一复位值。 采样电路允许第一复位值在第一次之后的第二时间衰减。 监视器电路被配置为响应于第二复位信号在第一时间将监视器节点驱动到第二复位值。 监视电路允许第二次复位值在第二次衰减。 当第二次监视节点衰减到预定的停止值时，监视电路第三次检测。