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40 条记录 (耗时 0.032 秒)

    Porting a circuit design from a first semiconductor process to a second semiconductor process
    1.
    发明授权
    Porting a circuit design from a first semiconductor process to a second semiconductor process 有权

    公开(公告)号：US08645878B1

    公开(公告)日：2014-02-04

    申请号：US13592122

    申请日：2012-08-22

    申请人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

    发明人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

    IPC分类号： G06F17/50

    CPC分类号： H01L21/22 ,  G06F17/505 ,  H01L21/266 ,  H01L29/7816

    摘要： Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

    Multiple cycle memory write completion
    4.
    发明授权
    Multiple cycle memory write completion 有权
    多周期内存写入完成

    公开(公告)号：US08446755B2

    公开(公告)日：2013-05-21

    申请号：US13369253

    申请日：2012-02-08

    申请人： Richard S. Roy

    发明人： Richard S. Roy

    IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1015 ,  G11C11/406 ,  G11C11/40618 ,  G11C2207/229

    摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

    摘要翻译： 一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。 在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。 随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。 可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。 可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

    Hierarchical Organization Of Large Memory Blocks
    5.
    发明申请
    Hierarchical Organization Of Large Memory Blocks 有权
    大内存块的分层结构

    公开(公告)号：US20110191564A1

    公开(公告)日：2011-08-04

    申请号：US12697132

    申请日：2010-01-29

    申请人： Richard S. Roy

    发明人： Richard S. Roy

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G11C11/408 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4096 ,  G11C11/4097

    摘要： A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency.

    摘要翻译： 多存储存储器系统包括一个或多个逻辑存储器层级以增加存储器系统的可用随机循环事务速率。 存储器系统包括多个多块分区，每个分区具有对应的分区接口。 每个分区接口以第一个频率访问相应的多存储体分区。 全局接口可以以等于第一个频率乘以分区接口数的第二个频率访问分区接口。 或者，多个集群接口可以访问分区接口的相应组，其中每个集群接口以比第一频率快的第二频率访问对应的分组接口组。 全局接口以大于第二个频率的第三个频率访问集群接口。

    Distributed interface for parallel testing of multiple devices using a single tester channel
    6.
    发明授权
    Distributed interface for parallel testing of multiple devices using a single tester channel 失效
    分布式接口，用于使用单个测试仪通道并行测试多个设备

    公开(公告)号：US06499121B1

    公开(公告)日：2002-12-24

    申请号：US09260463

    申请日：1999-03-01

    申请人： Richard S. Roy ,  Charles A. Miller

    发明人： Richard S. Roy ,  Charles A. Miller

    IPC分类号： G01R3128

    CPC分类号： G11C29/48 ,  G01R31/31905 ,  G01R31/31926 ,  G01R31/3193 ,  G11C29/56 ,  G11C2029/2602 ,  G11C2029/5606 ,  H01L2224/16225

    摘要： A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.

    摘要翻译： 一种用于测试许多被测试的集成电路（IC）器件（DUT）的系统，其具有耦合到单通道或多通道测试器的接口电路，用于从测试器接收数据值并提供关于DUT的错误信息。 接口电路将数据值（通过单个通道从测试仪接收）并行转发到多个DUT。 该电路使用从DUT读取的数据值执行比较，并且响应于产生指示比较的误差值。 然后可以通过相同或不同的通道将错误值返回给测试仪。

    Static ram with common data line equalization
    7.
    发明授权
    Static ram with common data line equalization 失效
    具有公共数据线均衡的静态RAM

    公开(公告)号：US4878198A

    公开(公告)日：1989-10-31

    申请号：US148279

    申请日：1988-01-25

    申请人： Richard S. Roy

    发明人： Richard S. Roy

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.

    摘要翻译： 一种具有多对公共数据线的静态随机存取存储器。 多个位线对耦合到每对公共数据输出线。 在每个存储器访问周期结束时，公共数据输出线自动均衡，并且在每个写入周期结束时，被访问的位线被自动均衡。 因此，将公共数据输出线均衡的过程从用于访问存储器的关键定时路径中移除，这消除了在静态存储器件中使用地址转换检测的主要问题之一。

    Semiconductor chip layout
    8.
    发明授权
    Semiconductor chip layout 有权
    半导体芯片布局

    公开(公告)号：US08901747B2

    公开(公告)日：2014-12-02

    申请号：US12846763

    申请日：2010-07-29

    申请人： Michael J. Miller ,  Mark Baumann ,  Richard S. Roy

    发明人： Michael J. Miller ,  Mark Baumann ,  Richard S. Roy

    IPC分类号： H01L29/40 ,  H01L23/50

    CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

    摘要翻译： 公开了一种用于高速半导体器件的芯片布局。 芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 串行接口位于中心位置，以减少延迟，功率和传播延迟。 包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

    Separate pass gate controlled sense amplifier
    10.
    发明授权
    Separate pass gate controlled sense amplifier 有权
    独立的通过门控制的读出放大器

    公开(公告)号：US08681574B2

    公开(公告)日：2014-03-25

    申请号：US13077798

    申请日：2011-03-31

    申请人： Richard S. Roy ,  Dipak K. Sikdar

    发明人： Richard S. Roy ,  Dipak K. Sikdar

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C2207/005

    摘要： A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

    摘要翻译： 存储器系统，其包括耦合到第一组动态随机存取存储器（DRAM）单元的第一位线，耦合到第二组DRAM单元的第二（互补）位线以及耦合到第一和第二 位线。 感测放大器包括耦合在第一和第二位线之间的一对交叉耦合的反相器（或类似的锁存电路）以及将第一位线耦合到第一全局位线的第一选择晶体管和第二选择 晶体管将第二位线耦合到第二全局位线。 第一和第二选择晶体管被独立地控制，从而能够实现改进的读和写访问序列，从而消除与位线耦合相关联的信号丢失，消除“读取凸起”条件，并消除后期写入条件。