公开(公告)号：US11770500B2

公开(公告)日：2023-09-26

申请号：US17587211

申请日：2022-01-28

Applicant: Microchip Technology Incorporated

Inventor： Lloyd Clark ,  Keith Curtis

IPC: H04N7/15 ,  H04L12/18 ,  H04N21/431 ,  H04N21/439 ,  H04N21/44 ,  H04N21/4788

CPC classification number: H04N7/15 ,  H04L12/1822 ,  H04N21/439 ,  H04N21/4312 ,  H04N21/44008 ,  H04N21/4788

Abstract: A system for managing a virtual meeting (e.g., video conference) includes memory storing a video conference application and at least one processor to execute the video conference application to generate a virtual meeting view for a first attendee including multiple attendee video streams arranged according to a virtual attendee arrangement specifying positions of the attendee video streams relative to each other in the virtual meeting view, receive second attendee audio data associated with a second attendee video stream, identify a particular video stream position specified by the virtual attendee arrangement, determine differential stereo effect data corresponding with the particular video stream position, and apply the differential stereo effect data to the second attendee audio data to provide differential audio signals on different audio channels output to the first attendee to create a stereo sound effect corresponding with the particular video stream position.

公开(公告)号：US20230291408A1

公开(公告)日：2023-09-14

申请号：US18181477

申请日：2023-03-09

Applicant: Microchip Technology Incorporated

Inventor： Siddhartha Hazra ,  Hormoz Djahanshahi

IPC: H03L7/099

CPC classification number: H03L7/0991

Abstract: One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

公开(公告)号：US11757550B2

公开(公告)日：2023-09-12

申请号：US17452661

申请日：2021-10-28

Applicant: Microchip Technology Incorporated

Inventor： Venkatraman Iyer ,  Dixon Chen ,  John Junling Zang ,  Shivanand I. Akkihal

IPC: H04J3/06

CPC classification number: H04J3/062

Abstract: Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

公开(公告)号：US11750243B2

公开(公告)日：2023-09-05

申请号：US17037919

申请日：2020-09-30

Applicant: Microchip Technology incorporated

Inventor： Marco Rohleder ,  Stefan Weiers

IPC: H04B3/54 ,  A24F40/65 ,  A24F40/90 ,  H02J7/00 ,  H03K17/687 ,  H03B5/20

CPC classification number: H04B3/54 ,  A24F40/65 ,  A24F40/90 ,  H02J7/0044 ,  H03K17/6871 ,  H03B5/20

Abstract: A system for transmitting power and data through a two pin connection interface may have a first device having a power source, a first microcontroller with a first communication peripheral coupled with a first pin and a first control port coupled with a gate of a first MOSFET whose switch path couples the power source with the first pin; and a second device having a battery, a second microcontroller with a second communication peripheral coupled with a first pin and a second control port coupled with a gate of a second MOSFET whose switch path couples the battery with the first pin of the second device. When the devices are coupled, the MOSFETs are synchronously turned on and off, wherein during an off-cycle a data transfer between the first and second device takes place through the first and second communication peripherals of the first and second device, respectively.

公开(公告)号：US20230273888A1

公开(公告)日：2023-08-31

申请号：US18108806

申请日：2023-02-13

Applicant: Microchip Technology Incorporated

Inventor： Andrew Rogers

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: An apparatus includes two PHY circuits, each including a PHY transmitter circuit and connected to a universal serial bus (USB)-C connector. The apparatus includes a USB circuit to issue a receiver detect signal through one of the PHY transmitters circuit to the USB-C connector, issue another receiver detect signal through the other PHY transmitter circuit to the USB-C connector, determine which receiver detect signal resulted in a termination in a USB-C element, and consequently determine an orientation of a USB plug connected between the apparatus and the USB-C element.

公开(公告)号：US11742005B2

公开(公告)日：2023-08-29

申请号：US17456819

申请日：2021-11-29

Applicant: Microchip Technology Incorporated

Inventor： Victor Nguyen

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/412

CPC classification number: G11C7/1084 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C11/417 ,  G11C11/4125

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

公开(公告)号：US20230268891A1

公开(公告)日：2023-08-24

申请号：US17664086

申请日：2022-05-19

Applicant: Microchip Technology Incorporated

Inventor： Henry Liang ,  Hongming An ,  James Ho ,  Congqing Xiong

IPC: H03F1/56 ,  H03F1/52

CPC classification number: H03F1/56 ,  H03F1/523 ,  H03F2200/264 ,  H03F2200/426

Abstract: This description relates, generally, to protecting a circuit from an input voltage. Various examples include an apparatus including one or more circuits to draw current from, or provide current to, a pair of connectors for an input circuit. The connectors may be for electrical coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative biasing signals. The apparatus may additionally include an operational amplifier to generate the positive and negative biasing signals. The operational amplifier may include: a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common-mode voltage of the input circuit. Related systems and methods are also disclosed.

公开(公告)号：US20230268376A1

公开(公告)日：2023-08-24

申请号：US17827648

申请日：2022-05-27

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L23/5226 ,  H01L23/5223 ,  H01L21/76877 ,  H01L21/76843 ,  H01L21/7687

Abstract: A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.

公开(公告)号：US20230260938A1

公开(公告)日：2023-08-17

申请号：US18141621

申请日：2023-05-01

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bony Chen ,  Yaojian Leng ,  Gerald Marsico ,  Julius Kovats

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/89 ,  H01L2224/0361 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05724 ,  H01L2224/05839 ,  H01L2224/08225 ,  H01L2224/80895

Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

公开(公告)号：US11723222B2

公开(公告)日：2023-08-08

申请号：US17074848

申请日：2020-10-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

IPC: H10K19/00 ,  H10K19/10 ,  H01L49/02

CPC classification number: H10K19/201 ,  H10K19/10 ,  H01L28/10

Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.