公开(公告)号：US20070002607A1

公开(公告)日：2007-01-04

申请号：US11172078

申请日：2005-06-29

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.

Abstract translation: 在一些实施例中，提供了包括SRAM位单元列的存储器阵列，每个列包括位线和耦合到位线的读出放大器，读出放大器在一段时间内维持其位线的选定单元格中的状态 读操作。 本文公开了其它实施例。

公开(公告)号：US20060267093A1

公开(公告)日：2006-11-30

申请号：US11429490

申请日：2006-05-04

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC: H01L27/12

CPC classification number: H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US20060187706A1

公开(公告)日：2006-08-24

申请号：US11008666

申请日：2005-02-22

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: G11C11/34

CPC classification number: G11C11/405 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

Abstract translation: 动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。 控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。 增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

公开(公告)号：US20060184595A1

公开(公告)日：2006-08-17

申请号：US11059174

申请日：2005-02-16

Applicant: James Tschanz ,  Mircea Stan ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

Inventor： James Tschanz ,  Mircea Stan ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

IPC: G06F15/00

CPC classification number: G06F13/4213 ,  H03K19/23 ,  H03M5/145 ,  Y02D10/14 ,  Y02D10/151

Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.

Abstract translation: 一般来说，在一个方面，本公开描述了一种包括代表性的多数选民门来分析多个位的位转换的装置。 分组的分类分析。 代表大多数选民门根据分析产生反转信号。 该装置进一步包括条件反相器将反相信号应用于多个位。

公开(公告)号：US20060139995A1

公开(公告)日：2006-06-29

申请号：US11027476

申请日：2004-12-28

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC: G11C11/34

CPC classification number: G11C17/146 ,  G11C17/12

Abstract: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.

Abstract translation: 一次性可编程存储器包括隔离栅极晶体管，其可以通过使隔离栅极晶体管受到降低隔离栅极晶体管特性的电压条件而被编程。 可以感测劣化的特性以读取存储器。

公开(公告)号：US20060098482A1

公开(公告)日：2006-05-11

申请号：US11289621

申请日：2005-11-30

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: G11C11/34

CPC classification number: H01L27/108 ,  G11C11/404

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

公开(公告)号：US20050285616A1

公开(公告)日：2005-12-29

申请号：US10880337

申请日：2004-06-29

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC: G01R19/165 ,  G01R31/26

CPC classification number: G01R31/2621 ,  G01R19/16571

Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

Abstract translation: 由于过电压状态，晶体管可能具有劣化特性。 可以感测劣化特性以确定晶体管先前已经经受过压状态。

公开(公告)号：US20050225459A1

公开(公告)日：2005-10-13

申请号：US10813084

申请日：2004-03-31

Applicant: Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

Inventor： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

IPC: G06F13/40 ,  H03M5/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US20050146921A1

公开(公告)日：2005-07-07

申请号：US10749734

申请日：2003-12-30

Applicant: Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

Inventor： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC: G11C11/24 ,  G11C11/405

CPC classification number: G11C11/405

Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.

Abstract translation: 双晶体管DRAM单元包括耦合到NMOS器件的NMOS器件和PMOS器件。

公开(公告)号：US20050145935A1

公开(公告)日：2005-07-07

申请号：US10750566

申请日：2003-12-31

Applicant: Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: G11C11/404 ,  H01L21/8239 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract translation: 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。