公开(公告)号：US06826082B2

公开(公告)日：2004-11-30

申请号：US10403739

申请日：2003-03-31

Applicant: Sang-Won Hwang ,  Sung-Soo Lee

Inventor： Sang-Won Hwang ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/3459 ,  G11C7/065 ,  G11C16/24

Abstract: Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.

Abstract translation: 可编程存储器件包括具有相关位线的存储单元。 缓冲电路将位线耦合到数据线。 缓冲电路具有耦合到位线的感测节点，并且包括具有耦合到数据线的锁存节点的锁存电路。 控制电路在存储器单元的编程操作与其对应的程序验证操作之间复位锁存节点。 存储器件可以是NAND型闪存器件，并且存储器单元可以是在位线和公共源极线之间串联连接的一串存储器单元之一。 晶体管可以将数据线耦合到锁存节点，并且晶体管可以将锁存器节点耦合到感测节点。 还提供了其操作方法。

公开(公告)号：US06717861B2

公开(公告)日：2004-04-06

申请号：US10006196

申请日：2001-12-04

Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.

Abstract translation: 公开了一种非易失性半导体存储器件，其包括根据位线设置，串选择线设置，编程周期的编程和放电周期来控制选择线和字线的电位的电路。 控制电路在编程周期中的位线建立期间将串选择线偏置为电源电压，并且在串选择线设置和程序周期期间将电源电压和接地电压之间的电压偏置。 根据串选择线控制方案，防止当将编程电压施加到与串选择线相邻的字线时在串选择线处感应到的噪声电压时的程序干扰。

公开(公告)号：US06614688B2

公开(公告)日：2003-09-02

申请号：US09990191

申请日：2001-11-20

Applicant: Jae-Yong Jeong ,  Jin-Seon Yeom ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Jin-Seon Yeom ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

公开(公告)号：US5986265A

公开(公告)日：1999-11-16

申请号：US921619

申请日：1997-09-02

Applicant: Tae-ho Kim ,  Sung-soo Lee

Inventor： Tae-ho Kim ,  Sung-soo Lee

IPC: G01V8/14 ,  G01J1/02 ,  G01J1/04 ,  G01J1/42 ,  G01J5/02 ,  G01J5/08 ,  G01J5/34 ,  G01S17/06 ,  G01V8/20 ,  G08B13/193 ,  G01J5/10

CPC classification number: G01J5/02 ,  G01J1/04 ,  G01J1/4228 ,  G01J5/025 ,  G01J5/026 ,  G01J5/06 ,  G01J5/08 ,  G01J5/0806 ,  G01J5/0846 ,  G01J5/0862 ,  G01J5/089 ,  G01J5/0893 ,  G08B13/193 ,  G01J1/0214 ,  G01J1/0271 ,  G01J5/0025

Abstract: Two pairs of pyroelectric devices are each mounted on a cone-shaped substrate to precisely control their alignment. Each cone-shaped substrate is a part of a sensor module which also supports an attenuator, along with a transistor and a resistor chip associated with each pyroelectric device of the pair. The sensor module is provided with a silicon filter through which infrared radiation is transmitted to the pair of pyroelectric devices. Each module is mounted in an inner space formed by two hemispherical lenses which serve to direct light to the module. Two such hemispherical lens-sensor modules are provided in a precise optical arrangement designed to operate in conjunction with associated circuitry in order to detect infrared radiation from any of six distinguishable zones. Applications of such a device include for example cameras and air conditioning systems.

Abstract translation: 两对热电装置分别安装在锥形基板上以精确控制其对准。 每个锥形衬底是传感器模块的一部分，其还支持衰减器，以及与该对中的每个热电装置相关联的晶体管和电阻器芯片。 传感器模块设置有硅过滤器，红外辐射通过该硅过滤器传送到一对热电装置。 每个模块安装在由用于将光引导到模块的两个半球透镜形成的内部空间中。 两个这样的半球形透镜传感器模块以精确的光学装置提供，设计成与相关联的电路结合操作，以便检测来自六个可区分区域中任何一个的红外辐射。 这种装置的应用包括例如照相机和空调系统。

公开(公告)号：US5634846A

公开(公告)日：1997-06-03

申请号：US636587

申请日：1996-04-23

Applicant: Sung-soo Lee ,  Tae-ho Kim ,  Won-kyo Jung

Inventor： Sung-soo Lee ,  Tae-ho Kim ,  Won-kyo Jung

IPC: G06M11/00 ,  F24F11/00 ,  F24F11/02 ,  G01J1/02 ,  G01V8/12 ,  G01V8/14 ,  G08B13/19 ,  G08B13/18

CPC classification number: F24F11/0034 ,  G08B13/19 ,  F24F2011/0036

Abstract: An object detector for an air conditioner has a signal detection input unit in which a light block is provided between a pair of Fresnel lenses spaced in parallel by a predetermined distance on a printed circuit board, thereby defining substantially three detection areas. The signal detection input unit detects the number, locations and movement distance of persons present indoor from a received signal, and outputs a signal representative of the information. Then, a command for the operation of an air conditioner is issued according to the information signal, thereby enabling the optimum operation of the air conditioner under circumstances.

Abstract translation: 一种用于空调的物体检测器具有信号检测输入单元，其中在一对在印刷电路板上间隔开预定距离的菲涅耳透镜之间设置有光块，从而基本上限定三个检测区域。 信号检测输入单元从接收信号中检测室内人员的数量，位置和移动距离，并输出表示信息的信号。 然后，根据信息信号发出空调机的运转命令，从而能够在情况下进行空调机的最佳运转。

公开(公告)号：US5548555A

公开(公告)日：1996-08-20

申请号：US420835

申请日：1995-04-11

Applicant: Sung-Soo Lee ,  Jin-Ki Kim

Inventor： Sung-Soo Lee ,  Jin-Ki Kim

IPC: G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC classification number: G11C29/785 ,  G11C29/24

Abstract: A method and a circuit for repairing defect by substituting a redundant memory cell for a defective memory cell in the semiconductor memory device. The circuit comprises charging nodes connected parallel to a number of electrical fuses; a device for outputting a storage signal of a defective address in response to an external control signal; a device for providing current to the charging node in response to the storage signal of the defective address; a redundant sense amplifier for outputting a redundant block driving signal to substitute a defective address in response to a logic level of the charging node; and a controller for decoding an address signal provided from the outside of the memory device so that a current path is formed in a selected fuse and the fuse is blew by current provided from the charging node, the controller being activated by the storage signal of the defective address.

Abstract translation: 一种用于通过在半导体存储器件中替换有缺陷存储单元的冗余存储单元来修复缺陷的方法和电路。 该电路包括与多个电保险丝并联连接的充电节点; 用于响应于外部控制信号输出缺陷地址的存储信号的装置; 用于响应于所述有缺陷地址的存储信号向所述计费节点提供电流的装置; 冗余感测放大器，用于响应于所述充电节点的逻辑电平输出冗余块驱动信号以代替缺陷地址; 以及控制器，用于对从存储器件的外部提供的地址信号进行解码，使得电流路径形成在所选择的熔丝中，并且熔丝被从充电节点提供的电流吹动，所述控制器由所述存储信号的存储信号激活 有缺陷的地址。

公开(公告)号：US09142799B2

公开(公告)日：2015-09-22

申请号：US13299311

申请日：2011-11-17

Applicant: Sung-Soo Lee ,  Ok-Keun Song ,  Se-II Kim

Inventor： Sung-Soo Lee ,  Ok-Keun Song ,  Se-II Kim

IPC: H05B33/10 ,  H01L51/52 ,  H01L27/32 ,  H01L51/50

Abstract: A light emitting structure includes a first hole injection layer, a first organic light emitting layer, a charge generation layer, a second hole injection layer, a second organic light emitting layer, an electron transfer layer, and a blocking member. The light emitting structure has first, second, and third sub-pixel regions. The first organic light emitting layer may be on the first hole injection layer. The charge generation layer may be on the first organic light emitting layer. The second hole injection layer may be on the charge generation layer. The second organic light emitting layer may be on the second hole injection layer. The electron transfer layer may be on the second organic light emitting layer. The blocking member may be at at least one of the first to the third sub-pixel regions.

公开(公告)号：US08330353B2

公开(公告)日：2012-12-11

申请号：US12326555

申请日：2008-12-02

Applicant: Jun-Ho Choi ,  Sung-Soo Lee ,  Chang-Mo Park ,  Seong-Min Kim

Inventor： Jun-Ho Choi ,  Sung-Soo Lee ,  Chang-Mo Park ,  Seong-Min Kim

IPC: H01J1/62

CPC classification number: H01L51/5203 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/3213 ,  H01L27/322 ,  H01L27/3248 ,  H01L27/3258 ,  H01L51/5271

Abstract: The present invention relates to an organic light emitting device including a substrate, an insulating layer disposed on the substrate, a first electrode disposed on the insulating layer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member. The insulating layer includes a furrow corresponding to at least one edge of the first electrode, and at least a portion of the second electrode is disposed in the furrow.

Abstract translation: 本发明涉及一种有机发光器件，其包括衬底，设置在衬底上的绝缘层，设置在绝缘层上的第一电极，设置在第一电极上的有机发光部件和设置在有机器件上的第二电极 发光部件。 绝缘层包括对应于第一电极的至少一个边缘的沟槽，并且第二电极的至少一部分设置在沟槽中。

公开(公告)号：US20120150478A1

公开(公告)日：2012-06-14

申请号：US13325154

申请日：2011-12-14

Applicant: Ki-Jae Song ,  Sung-Soo Lee

Inventor： Ki-Jae Song ,  Sung-Soo Lee

IPC: G06F19/00 ,  H01L21/66 ,  G01R31/26

CPC classification number: G01R31/31908 ,  G01R31/318513 ,  G01R31/31919

Abstract: In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.

Abstract translation: 在测试对象的方法中，可以在测试器中设置用于测试对象中的第一设备的第一测试模式。 用于测试物体中的第二装置的第二测试图案可以设置在电连接在测试器和物体之间的测试头中。 可以通过测试头将第一测试图案提供给第一设备，并且可以由测试头将第二测试图案提供给第二设备，以同时测试第一设备和第二设备。 因此，可以在不改变测试器中的测试条件的情况下同时测试彼此不同的第一设备和第二设备，从而可以减少测试对象的时间。

公开(公告)号：US20120108035A1

公开(公告)日：2012-05-03

申请号：US13228966

申请日：2011-09-09

Applicant: Goon-Woo Kim ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Jeong-sam Lee ,  Sung-Soo Lee

Inventor： Goon-Woo Kim ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Jeong-sam Lee ,  Sung-Soo Lee

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B23K26/364 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/67092 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

Abstract: A method of fabricating a semiconductor device includes preparing a semiconductor wafer having a top surface and a bottom surface. The semiconductor wafer is loaded onto a wafer chuck, and the bottom surface of the loaded semiconductor wafer faces the wafer chuck. A groove is formed in the top surface of the loaded semiconductor wafer by irradiating a second laser onto the top surface, and a reforming region is formed in the loaded semiconductor wafer under the groove by irradiating a first laser through wafer chuck and bottom surface of the semiconductor wafer into a region in which the first laser is focused. The semiconductor wafer is unloaded from the wafer chuck. The bottom surface of the semiconductor wafer is ground to decrease a thickness of the semiconductor wafer. The semiconductor wafer is separated along the groove and the reforming region, thereby forming a plurality of unit chips.

Abstract translation: 制造半导体器件的方法包括制备具有顶表面和底表面的半导体晶片。 将半导体晶片装载到晶片卡盘上，并且加载的半导体晶片的底表面面向晶片卡盘。 通过将第二激光照射在顶面上，在负载的半导体晶片的顶面形成有槽，通过将晶片卡盘的第一激光照射到晶片卡盘的下表面， 半导体晶片进入第一激光器聚焦的区域。 半导体晶片从晶片卡盘卸载。 研磨半导体晶片的底面以减小半导体晶片的厚度。 半导体晶片沿着沟槽和重整区域分离，从而形成多个单元芯片。