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公开(公告)号：US11200384B2
公开(公告)日：2021-12-14
申请号：US16817496
申请日：2020-03-12
Applicant: Arm Limited
Abstract: Disclosed are methods, systems and devices for allocating a power signal. In one particular implementation, a reader device may exchange messages with one more transponder devices to determine an allocation of a power signal. For example, one or more transponder devices may provide one or more messages in a downlink signal indicative of a requested signal up time.
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公开(公告)号：US10777273B2
公开(公告)日：2020-09-15
申请号：US15781961
申请日：2016-11-29
Applicant: Arm Limited
Inventor： Shidhartha Das , James Edward Myers , Seng Oon Toh
Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.
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公开(公告)号：US10664031B2
公开(公告)日：2020-05-26
申请号：US15361405
申请日：2016-11-26
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , Bal S. Sandhu , James Edward Myers , Alexander Stewart Weddell , David Walter Flynn
IPC: G06F1/00 , G06F1/28 , G01R19/165
Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.
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公开(公告)号：US10651683B2
公开(公告)日：2020-05-12
申请号：US15313599
申请日：2015-05-11
Applicant: ARM Limited
Abstract: An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry 56 or the at least one harvesting unit 52 to reduce impedance mismatch between an output impedance of the harvesting unit 52 and an input impedance of the at least one circuit 54.
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公开(公告)号：US20200089266A1
公开(公告)日：2020-03-19
申请号：US16130938
申请日：2018-09-13
Applicant: Arm Limited
IPC: G05F3/24 , G05F1/46 , G11C5/14 , G11C11/4074
Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power
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Patent Agency Ranking
公开(公告)号：US10586790B2
公开(公告)日：2020-03-10
申请号：US15942132
申请日：2018-03-30
Applicant: Arm Limited
Inventor： Pranay Prabhat , James Edward Myers
IPC: H01L27/02 , G11C11/417 , G11C11/412 , H01L27/11
Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.
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公开(公告)号：US10303906B1
公开(公告)日：2019-05-28
申请号：US15825467
申请日：2017-11-29
Applicant: Arm Limited
Inventor： James Edward Myers , David Michael Bull , Edgar H. Callaway, Jr.
Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.
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公开(公告)号：US10191527B2
公开(公告)日：2019-01-29
申请号：US14712614
申请日：2015-05-14
Applicant: ARM Limited
Inventor： Bal S. Sandhu , James Edward Myers
IPC: G01R31/40 , G01R19/165 , G06F1/28 , G01R19/32
Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.
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公开(公告)号：US20180278244A1
公开(公告)日：2018-09-27
申请号：US15990538
申请日：2018-05-25
Applicant: ARM Limited , University of Southampton
Inventor： Anand Savanth , James Edward Myers , Yunpeng Cai , Alexander Stewart Weddell , Tom Kazmierski
IPC: H03K3/3562 , H03K19/20
CPC classification number: H03K3/35625 , H03K19/20
Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
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公开(公告)号：US09940993B2
公开(公告)日：2018-04-10
申请号：US15093457
申请日：2016-04-07
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC: G11C5/06 , G11C11/419
CPC classification number: G11C11/419 , G11C5/063 , G11C11/4125
Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
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