公开(公告)号：US07407891B2

公开(公告)日：2008-08-05

申请号：US11268356

申请日：2005-11-07

申请人： Theresia Bauer ,  Robert Hoelzl ,  Andreas Huber ,  Reinhold Wahlich

发明人： Theresia Bauer ,  Robert Hoelzl ,  Andreas Huber ,  Reinhold Wahlich

IPC分类号： H01L21/302

CPC分类号： H01L21/30604 ,  H01L21/02019 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.

摘要翻译： 通过晶片表征参数的位置相关测量对半导体晶片进行调平，以在半导体晶片的整个表面上确定该参数的位置相关值，同时在蚀刻介质的作用下蚀刻半导体晶片的整个表面 随着整个表面的同时照明，材料去除蚀刻速率取决于半导体晶片表面处的光强度，光强度以位置相关的方式被建立，使得位置相关值的差异 在步骤a）中测量的参数被依赖于位置的材料去除率降低。 通过该方法产生具有改善的平坦度和纳米形貌的半导体晶片和具有改善的层厚均匀性的SOI晶片。

公开(公告)号：US20080122043A1

公开(公告)日：2008-05-29

申请号：US12023102

申请日：2008-01-31

申请人： Markus Blietz ,  Robert Hoelzl ,  Reinhold Wahlich ,  Andreas Huber

发明人： Markus Blietz ,  Robert Hoelzl ,  Reinhold Wahlich ,  Andreas Huber

IPC分类号： H01L23/58 ,  H01L21/02

CPC分类号： H01L21/2007

摘要： Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

摘要翻译： 直径为至少200mm的半导体晶片包括硅载体晶片，电绝缘层和位于其上的半导体层，半导体晶片已经通过包括至少一个RTA步骤的层转移工艺生产，其中半导体 晶片具有小于30μm的翘曲，小于30μm的DeltaWarp，小于10μm的弓和小于10um的DeltaBow。 用于生产这种类型的半导体晶片的方法需要特定的热处理方案。

公开(公告)号：US20080059919A1

公开(公告)日：2008-03-06

申请号：US11936673

申请日：2007-11-07

申请人： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

发明人： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC分类号： G06F17/50

CPC分类号： H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

摘要翻译： 用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

公开(公告)号：US20080026232A1

公开(公告)日：2008-01-31

申请号：US11828392

申请日：2007-07-26

申请人： Dieter Knerer ,  Andreas Huber ,  Ulrich Lambert ,  Friedrich Passek

发明人： Dieter Knerer ,  Andreas Huber ,  Ulrich Lambert ,  Friedrich Passek

IPC分类号： B32B15/04 ,  H01L21/268

CPC分类号： H01L21/268 ,  H01L29/32 ,  Y10T428/24802 ,  Y10T428/31678

摘要： Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm2 to 0.1/cm2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m2 to 10 GW/m2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.

摘要翻译： 单晶半导体晶片具有缺陷减少区域，缺陷减少区域具有在0 / cm 2至0.1 / cm 2范围内的GOI相关缺陷密度，以及 占据半导体晶片的平面面积的10％至100％的总面积比，其中半导体晶片的其余区域具有比缺陷减少区域明显更高的缺陷密度。 可以通过用于通过用激光照射半导体晶片的侧面的限定区域来对晶片中的GOI相关缺陷进行退火的方法来生产晶片，其中每个位置以1GW / m 2的功率密度照射， SUP>至10GW / m 2至少25ms，其中激光器发射波长在晶片半导体材料的吸收边缘上方的波长，并且其中晶片的温度升高小于20 K作为照射的结果。

公开(公告)号：US20070283172A1

公开(公告)日：2007-12-06

申请号：US11420820

申请日：2006-05-30

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC分类号： G06F1/00

CPC分类号： G06F1/26

摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

摘要翻译： 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

公开(公告)号：US20070260444A1

公开(公告)日：2007-11-08

申请号：US11380058

申请日：2006-04-25

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Gia-Harvey Truong ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Gia-Harvey Truong ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of power delivery analysis and design for a hierarchical system including building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, assembling a system model from the models contained in the repository, flattening the system model, and running a simulation on the flattened system model.

摘要翻译： 一种用于分层系统的功率传递分析和设计的方法，包括构建与分层系统的每个元件相对应的模型，编译包含与分层系统的每个元件相对应的模型的存储库，从包含的模型组装系统模型 存储库，平整系统模型，并在平面化系统模型上运行仿真。

公开(公告)号：US20070239387A1

公开(公告)日：2007-10-11

申请号：US11278848

申请日：2006-04-06

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

IPC分类号： G06F19/00

CPC分类号： G01R19/16552

摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. In embodiments of the invention, only a single pair of C4 pins is required for all voltage monitoring activity. One useful embodiment is directed to apparatus for monitoring the level of voltage associated with each domain in a partitioned chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.

摘要翻译： 提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。 在本发明的实施例中，对于所有电压监视活动，仅需要一对C4引脚。 一个有用的实施例涉及用于监视与分区芯片中的每个域相关联的电压电平的装置。 该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平 的多个电压域中的两个。 设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且电子芯片外部的传感器装置被连接以测量所监视的相应的多个 电压域使用单个导电链路。

公开(公告)号：US07266788B2

公开(公告)日：2007-09-04

申请号：US11184350

申请日：2005-07-19

申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

IPC分类号： G06F17/50

CPC分类号： H01L23/49833 ,  G06F17/5068 ,  H01L23/50 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

公开(公告)号：US20060272851A1

公开(公告)日：2006-12-07

申请号：US11146441

申请日：2005-06-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US07075253B2

公开(公告)日：2006-07-11

申请号：US10845139

申请日：2004-05-14

申请人： Andreas Huber

发明人： Andreas Huber

IPC分类号： G05F1/00

CPC分类号： H05B41/295 ,  H05B37/0254 ,  Y10S315/07

摘要： In an operating method for a lighting system and a lighting system in which a readiness command is provided, in response to such readiness command a ballast drives a discharge lamp in such a way that it heats the electrodes further if the discharge lamp is not burning, so that a controller can use a switch-on command to reignite the discharge lamp without delay by means of a preheating time.

摘要翻译： 在其中提供准备命令的照明系统和照明系统的操作方法中，响应于这种准备命令，镇流器以如下方式驱动放电灯，使得如果放电灯不燃烧则进一步加热电极， 使得控制器可以使用接通命令通过预热时间而不延迟地点燃放电灯。